Abstract is missing.
- 3D VLSI: A Scalable Integration Beyond 2DKarim Arabi, Kambiz Samadi, Yang Du. 1-7 [doi]
- BonnPlace: A Self-Stabilizing Placement FrameworkUlrich Brenner, Anna Hermann, Nils Hoppmann, Philipp Ochsendorf. 9-16 [doi]
- Coarse-grained Structural Placement for a Synthesized Parallel MultiplierSungmin Bae, Hyung-Ock Kim, Jung Yun Choi, Jaehong Park. 17-24 [doi]
- Common-Centroid FinFET Placement Considering the Impact of Gate MisalignmentPo-Hsun Wu, Mark Po-Hung Lin, Xin Li, Tsung-Yi Ho. 25-31 [doi]
- Automation of Analog IC Layout: Challenges and SolutionsJürgen Scheible, Jens Lienig. 33-40 [doi]
- Q-Learning Based Dynamic Voltage Scaling for Designs with Graceful DegradationYu-Guang Chen, Wan-yu Wen, Tao Wang, Yiyu Shi, Shih-Chieh Chang. 41-48 [doi]
- SVM-Based Routability-Driven Chip-Level Design for Voltage-Aware Pin-Constrained EWOD ChipsQin Wang, Weiran He, Hailong Yao, Tsung-Yi Ho, Yici Cai. 49-56 [doi]
- Machine Learning in Simulation-Based AnalysisLi-C. Wang, Malgorzata Marek-Sadowska. 57-64 [doi]
- Physical Layout Design of Directed Self-Assembly Guiding Alphabet for IC Contact Hole/via PatterningH.-S. Philip Wong, He Yi, Maryann Tung, Kye Okabe. 65-66 [doi]
- A Cell-Based Row-Structure Layout Decomposer for Triple Patterning LithographyHsi-An Chien, Szu-Yuan Han, Ye Hong Chen, Ting-Chi Wang. 67-74 [doi]
- TPL-Aware Displacement-driven Detailed Placement Refinement with Coloring ConstraintsTao Lin, Chris C. N. Chu. 75-80 [doi]
- Concept & Research to Revenue: An Entrepreneurial StoryDean Drako. 81 [doi]
- Analog Circuit and Layout Synthesis RevisitedRob A. Rutenbar. 83 [doi]
- A Useful Skew Tree Framework for Inserting Large Safety MarginsRickard Ewetz, Cheng-Kok Koh. 85-92 [doi]
- Analytical Clustering Score with Application to Post-Placement Multi-Bit Flip-Flop MergingChang Xu, Peixin Li, Guojie Luo, Yiyu Shi, Iris Hui-Ru Jiang. 93-100 [doi]
- Physical Design Challenges in the Chip Power Distribution NetworkFarid N. Najm. 101 [doi]
- Accelerated Path-Based Timing Analysis with MapReduceTsung-Wei Huang, Martin D. F. Wong. 103-110 [doi]
- Blech Effect in Interconnects: Applications and Design GuidelinesAli Abbasinasab, Malgorzata Marek-Sadowska. 111-118 [doi]
- On Resilient System Performance BinningQiang Han, Jianghao Guo, Qiang Xu, Wen-Ben Jone. 119-125 [doi]
- From 2D to Monolithic 3D: Design Possibilities, Expectations and ChallengesOlivier Billoint, Hossam Sarhan, Iyad Rayane, Maud Vinet, Perrine Batude, Claire Fenouillet-Béranger, Olivier Rozeau, Gerald Cibrario, Fabien Deprat, Ogun Turkyilmaz, Sebastien Thuries, Fabien Clermidy. 127 [doi]
- Early Days of Circuit PlacementMartin D. F. Wong. 129 [doi]
- Force-Directed Placement of VLSI CircuitsHans Eisenmann. 131-132 [doi]
- Beyond GORDIAN and Kraftwerk: EDA Research at TUMUlf Schlichtmann. 133-140 [doi]
- Timing-Driven Placement Based on Dynamic Net-Weighting for Efficient Slack Histogram CompressionChrystian Guth, Vinicius S. Livramento, Renan Netto, Renan Fonseca, José Luís Güntzel, Luiz C. V. dos Santos. 141-148 [doi]
- Closing the Gap between Global and Detailed Placement: Techniques for Improving RoutabilityChun-Kai Wang, Chuan-Chia Huang, Shih-Ying Sean Liu, Ching-Yu Chin, Sheng-Te Hu, Wei-Chen Wu, Hung-Ming Chen. 149-156 [doi]
- ISPD 2015 Benchmarks with Fence Regions and Routing Blockages for Detailed-Routing-Driven PlacementIsmail S. Bustany, David G. Chinnery, Joseph R. Shinnerl, Vladimir Yutsis. 157-164 [doi]
- FreePDK15: An Open-Source Predictive Process Design Kit for 15nm FinFET TechnologyKirti Bhanushali, W. Rhett Davis. 165-170 [doi]
- Open Cell Library in 15nm FreePDK TechnologyMayler G. A. Martins, Jody Maick Matos, Renato P. Ribas, André Inácio Reis, Guilherme Schlinker, Lucio Rech, Jens Michelsen. 171-178 [doi]
- Design Rule Management and its Applications in 15nm FreePDK TechnologyMichiel Oostindie, Coby Zelnik, Maarten Berkens. 179-183 [doi]
- A Benchmark Suite to Jointly Consider Logic Synthesis and Physical DesignJody Maick Matos, Augusto Neutzling, Renato P. Ribas, André Inácio Reis. 185-192 [doi]