Abstract is missing.
- Scalable System and Silicon Architectures to Handle the Workloads of the Post-Moore EraIvo Bolsens. 1-2 [doi]
- Placement Optimization with Deep Reinforcement LearningAnna Goldie, Azalia Mirhoseini. 3-7 [doi]
- Hill Climbing with Trees: Detail Placement for Large WindowsMohammad Khasawneh, Patrick H. Madden. 9-16 [doi]
- Via Pillar-aware Detailed PlacementYong Zhong, Tao-Chun Yu, Kai-Chuan Yang, Shao-Yun Fang. 17-24 [doi]
- Soft-Clustering Driven Flip-flop Placement Targeting Clock-induced OCVDimitrios Mangiras, Pavlos M. Mattheakis, Pierre-Olivier Ribet, Giorgos Dimitrakopoulos. 25-32 [doi]
- Advances in Carbon Nanotube Technologies: From Transistors to a RISC-V MicroprocessorGage Hills, Christian Lau, Tathagata Srimani, Mindy D. Bishop, Pritpal Kanhaiya, Rebecca Ho, Aya G. Amer, Max M. Shulaker. 33-38 [doi]
- Full-Chip Electro-Thermal Coupling Extraction and Analysis for Face-to-Face Bonded 3D ICsLingjun Zhu, Kyungwook Chang, Dusan Petranovic, Saurabh Sinha, Yun Seop Yu, Sung Kyu Lim. 39-46 [doi]
- Pseudo-3D Approaches for Commercial-Grade RTL-to-GDS Tool Flow Targeting Monolithic 3D ICsHeechun Park, Bon Woong Ku, Kyungwook Chang, Da Eun Shim, Sung Kyu Lim. 47-54 [doi]
- Learning from Experience: Applying ML to Analog Circuit DesignKishor Kunal, Tonmoy Dhar, Yaguang Li, Meghna Madhusudan, Jitesh Poojary, Arvind K. Sharma, Wenbin Xu, Steven M. Burns, Ramesh Harjani, Jiang Hu, Parijat Mukherjee, Sachin S. Sapatnekar. 55 [doi]
- Transforming Global Routing Report into DRC Violation Map with Convolutional Neural NetworkWei-Tse Hung, Jun-Yang Huang, Yih-Chih Chou, Cheng-Hong Tsai, Mango Chia-Tso Chao. 57-64 [doi]
- Lookahead Placement Optimization with Cell Library-based Pin Accessibility Prediction via Active LearningTao-Chun Yu, Shao-Yun Fang, Hsien-Shih Chiu, Kai-Shun Hu, Philip Hui-Yuh Tai, Cindy Chin-Fang Shen, Henry Sheng. 65-72 [doi]
- Physical Design for 3D Chiplets and System IntegrationCliff Hou. 73 [doi]
- Hardware Security For and Beyond CMOS Technology: An Overview on Fundamentals, Applications, and ChallengesJohann Knechtel. 75-86 [doi]
- Design Optimization by Fine-grained Interleaving of Local Netlist Transformations in Lagrangian RelaxationApostolos Stefanidis, Dimitrios Mangiras, Chrysostomos Nicopoulos, David G. Chinnery, Giorgos Dimitrakopoulos. 87-94 [doi]
- Selective Sensor Placement for Cost-Effective Online Aging Monitoring and ResilienceHao-Chun Chang, Li-An Huang, Kai-Chiang Wu, Yu-Guang Chen. 95-102 [doi]
- Synthesis of Clock Networks with a Mode Reconfigurable Topology and No Short Circuit CurrentNecati Uysal, Juan Ariel Cabrera, Rickard Ewetz. 103-110 [doi]
- Timing Driven Partition for Multi-FPGA Systems with TDM AwarenessSin-Hong Liou, Sean S.-Y. Liu, Richard Sun, Hung-Ming Chen. 111-118 [doi]
- Understanding Graphs in EDA: From Shallow to Deep LearningYuzhe Ma, Zhuolun He, Wei Li, Lu Zhang, Bei Yu 0001. 119-126 [doi]
- TEMPO: Fast Mask Topography Effect Modeling with Deep LearningWei Ye, Mohamed Baker Alawieh, Yuki Watanabe, Shigeki Nojima, Yibo Lin, David Z. Pan. 127-134 [doi]
- DRC Hotspot Prediction at Sub-10nm Process Nodes Using Customized Convolutional NetworkRongjian Liang, Hua Xiang, Diwesh Pandey, Lakshmi N. Reddy, Shyam Ramji, Gi-Joon Nam, Jiang Hu. 135-142 [doi]
- Physical Verification at Advanced Technology Nodes and the Road AheadJuan C. Rey. 143 [doi]
- ISPD 2020 Physical Mapping of Neural Networks on a Wafer-Scale Deep Learning AcceleratorMichael James, Marvin Tom, Patrick Groeneveld, Vladimir Kibardin. 145-149 [doi]