Table of Contents

• Application Profiling Using Register-Instruction Hardware Performance CountersAnand Menon, Amisha Srivastava, Shamik Kundu, Kanad Basu. 1-6 [doi]
• X4-RARE: Revisiting the X4CP32 Coarse-Grained Reconfigurable Architecture ModelIvan Saraiva Silva, Francisco Carlos Silva Junior. 1-6 [doi]
• Design-Space Exploration of Multiplier Approximation in CNNsS. N. Raghava, Prashanth H. C., Bindu G. Gowda, Pratyush Nandi, Madhav Rao. 1-6 [doi]
• Machine Learning Techniques for Pre-CTS Identification of Timing Critical Flip-FlopsChunkai Fu, Ben Trombley, Hua Xiang 0001, Gi-Joon Nam, Jiang Hu. 1-6 [doi]
• Dynamic Offloading for Improved Performance and Energy Efficiency in Heterogeneous IoT-Edge-Cloud ContinuumJulio Costella Vicenzi, Guilherme Korol, Michael Guilherme Jordan, Wagner Ourique de Morais, Hazem Ali, Edison Pignaton de Freitas, Mateus Beck Rutzig, Antonio Carlos Schneider Beck. 1-6 [doi]
• Harnessing the Effects of Process Variability to Mitigate Aging in Cloud ServersArthur Francisco Lorenzon, Guilherme Korol, Marcelo Brandalero, Antonio Carlos Schneider Beck. 1-6 [doi]
• Column-Weighted Probabilistic GDBF Decoder for Irregular LDPC CodesChangfu He, Keyue Deng, Suwen Song, Zhongfeng Wang 0001. 1-6 [doi]
• tubGEMM: Energy-Efficient and Sparsity-Effective Temporal-Unary-Binary Based Matrix Multiply UnitPrabhu Vellaisamy, Harideep Nair, Joseph Finn, Manav Trivedi, Albert Chen, Anna Li, Tsung-Han Lin, Perry H. Wang, Ronald Shawn Blanton, John Paul Shen. 1-6 [doi]
• Resource Provisioning for CPU-FPGA Environments with Adaptive HLS-Versioning and DVFSMichael Guilherme Jordan, Guilherme Korol, Tiago Knorst, Mateus Beck Rutzig, Antonio Carlos Schneider Beck. 1-6 [doi]
• An Investigation into the Security of Register Allocation with Spilling and SplittingPriyanka Panigrahi, Chandan Karfa. 1-6 [doi]
• Grep: Performance Enhancement in MultiCore Processors using an Adaptive Graph PrefetcherIndranee Kashyap, Dipika Deb, Nityananda Sarma. 1-6 [doi]
• Evaluating an XOR-based Hybrid Fault Tolerance Technique to Detect Faults in GPU PipelinesGiani Augusto Braga, Marcio M. Gonçalves, José Rodrigo Azambuja. 1-6 [doi]
• Using Lyapunov Exponents and Entropy to Estimate Sensitivity to Process VariabilityElias de Almeida Ramos, Ricardo Reis 0001. 1-6 [doi]
• Design Exploration of Dynamic Multi-Level Ternary Content-Addressable Memory Using Nanoelectromechanical RelaysTaixin Li, Hongtao Zhong, Sumitha George, Vijaykrishnan Narayanan, Liang Shi, Huazhong Yang, Xueqing Li. 1-6 [doi]
• Benchmarking of SoC-Level Hardware Vulnerabilities: A Complete WalkthroughShams Tarek, Hasan Al Shaikh, Sree Ranjani Rajendran, Farimah Farahmandi. 1-6 [doi]
• Evaluation of Digital Circuit Design by Combining Two - and Multi-Level Approximate Logic SynthesisGabriel Ammes, Paulo F. Butzen, André Inácio Reis, Renato P. Ribas. 1-6 [doi]
• Design and Evaluation of M-Term Non-Homogeneous Hybrid Karatsuba Polynomial MultiplierSanampudi Gopala Krishna Reddy, Gogireddy Ravi Kiran Reddy, D. R. Vasanthi, Madhav Rao. 1-6 [doi]
• 3D-TTP: Efficient Transient Temperature-Aware Power Budgeting for 3D-Stacked Processor-Memory SystemsSobhan Niknam, Yixian Shen, Anuj Pathania, Andy D. Pimentel. 1-6 [doi]
• A Secure Design Methodology to Prevent Targeted Trojan Insertion during FabricationArjun Suresh, Siva Nishok Dhanuskodi, Daniel E. Holcomb. 1-6 [doi]
• iTPM: Exploring PUF-based Keyless TPM for Security-by-Design of Smart ElectronicsVenkata K. V. V. Bathalapalli, Saraju P. Mohanty, Elias Kougianos, Vasanth Iyer, Bibhudutta Rout. 1-6 [doi]
• LAT-UP: Exposing Layout-Level Analog Hardware Trojans Using Contactless Optical ProbingSajjad Parvin, Mehran Goli, Thilo Krachenfels, Shahin Tajik, Jean-Pierre Seifert, Frank Sill Torres, Rolf Drechsler. 1-6 [doi]
• Reverse Engineering of RTL Controllers from Look-Up Table NetlistsSundarakumar Muthukumaran, Aparajithan Nathamuni Venkatesan, Kishore Pula, Ram Venkat Narayanan, Ranga Vemuri, John Marty Emmert. 1-6 [doi]
• CWAHA: Cluster-Wise Approximation for Hardware implementation of Arithmetic functionsOmkar G. Ratnaparkhi, Madhav Rao. 1-6 [doi]
• CellFlow: Automated Standard Cell Design FlowPrashanth H. C., Prashanth Jonna, Madhav Rao. 1-5 [doi]
• A MCU-robust Interleaved Data/Detection SRAM for Space EnvironmentsLeonardo Heitich Brendler, Hervé Lapuyade, Yann Deval, Ricardo Reis 0001, François Rivet. 1-6 [doi]
• A Digital SRAM Computing-in-Memory Design Utilizing Activation Unstructured Sparsity for High-Efficient DNN InferenceBaiqing Zhong, Mingyu Wang, Chuanghao Zhang, Yangzhan Mai, Xiaojie Li, Zhiyi Yu. 1-6 [doi]
• Fortified-Edge 2.0: Machine Learning based Monitoring and Authentication of PUF-Integrated Secure Edge Data CenterSeema G. Aarella, Saraju P. Mohanty, Elias Kougianos, Deepak Puthal. 1-6 [doi]
• Formal Temporal Characterization of Register Vulnerability in Digital CircuitsDamiano Zuccalà, Jean-Marc Daveau, Philippe Roche, Katell Morin-Allory. 1-6 [doi]
• Versatile Signal Distribution Networks for Scalable Placement and Routing of Field-coupled Nanocomputing TechnologiesMarcel Walter, Benjamin Hien, Robert Wille. 1-6 [doi]
• Machine Learning and Polynomial Chaos models for Accurate Prediction of SET Pulse CurrentVishu Saxena, Yash Jain, Sparsh Mittal. 1-6 [doi]
• Compact Model Parameter Extraction using Bayesian Machine LearningSachin Bhat, Sourabh Kulkarni, Csaba Andras Moritz. 1-6 [doi]
• L-BANCS: A Multi-Phase Tile Design for Nanomagnetic LogicRuan Evangelista Formigoni, Ricardo S. Ferreira 0001, Omar P. Vilela Neto, José Augusto Miranda Nacif. 1-6 [doi]
• IoMT Synthetic Cardiac Arrest Dataset for eHealth with AI-based ValidationJoy Dutta, Deepak Puthal. 1-6 [doi]
• DREAM: Distributed Reinforcement Learning Enabled Adaptive Mixed-Critical NoCNidhi Anantharajaiah, Yunhe Xu, Fabian Lesniak, Tanja Harbaum, Jürgen Becker 0001. 1-6 [doi]
• Efficient Accelerator Design in High-Level Synthesis Using Approximate Logic ComponentsTiago da Silva Almeida, Lucas Wanner 0001. 1-6 [doi]
• Modeling and Analysis of Switched-Capacitor Converters as a Multi-port Network for Covert CommunicationYerzhan Mustafa, Selçuk Köse. 1-6 [doi]
• Performance Optimized Clock Tree Embedding for Auto-Generated FPGAsGrant Brown, Ganesh Gore, Pierre-Emmanuel Gaillardon. 1-6 [doi]
• An FPGA-Based Reconfigurable CNN Training Accelerator Using Decomposable WinogradHui Wang, Jinming Lu, Jun Lin, Zhongfeng Wang 0001. 1-6 [doi]
• A Compact Ferroelectric 2T-(n+1)C Cell to Implement AND-OR Logic in MemoryYi Xiao, Yixin Xu, Shan Deng, Zijian Zhao, Sumitha George, Kai Ni 0004, Vijaykrishnan Narayanan. 1-6 [doi]
• Power, Performance and Reliability Evaluation of Multi-thread Machine Learning Inference Models Executing in Multicore Edge DevicesGeancarlo Abich, Anderson Ignacio da Silva, José Eduardo Thums, Rafael da Silva, Altamiro Amadeu Susin, Ricardo Reis 0001, Luciano Ost. 1-6 [doi]
• Exploiting Routing Asymmetry for APUF Implementation in FPGA: A Proof-of-ConceptTrishna Rajkumar. 1-4 [doi]
• Revolutionizing Cyber Security: Exploring the Synergy of Machine Learning and Logical Reasoning for Cyber Threats and MitigationDeepak Puthal, Saraju P. Mohanty, Amit Kumar Mishra, Chan Yeob Yeun, Ernesto Damiani. 1-6 [doi]
• Robustness and Power Efficiency in Spin-Orbit Torque-Based Probabilistic Logic CircuitsKamal Danouchi, Guillaume Prenat, Philippe Talatchian, Louis Hutin, Lorena Anghel. 1-6 [doi]
• A 3 TOPS/W RISC-V Parallel Cluster for Inference of Fine-Grain Mixed-Precision Quantized Neural NetworksAlessandro Nadalini, Georg Rutishauser, Alessio Burrello, Nazareno Bruschi, Angelo Garofalo, Luca Benini, Francesco Conti 0001, Davide Rossi. 1-6 [doi]
• Federated Learning with Spiking Neural Networks in Heterogeneous SystemsSadia Anjum Tumpa, Sonali Singh, Md Fahim Faysal Khan, Mahmut Taylan Kandemir, Vijaykrishnan Narayanan, Chita R. Das. 1-6 [doi]
• FastNTT: Design and Evaluation of Modular-Reduction Based Fast NTT Design on FPGAHarshita Gupta, Mayank Kabra, Asmita Zjigyasu, Madhav Rao. 1-6 [doi]
• Efficient Hardware Design for the VVC Affine Motion Compensation Exploiting Multiple Constant MultiplicationMarcello M. Muñoz, Denis Maass, Murilo R. Perleberg, Luciano Agostini, Marcelo Schiavon Porto. 1-6 [doi]
• Photonic Convolution Engine Based on Phase-Change Materials and Stochastic ComputingRaphael Cardoso, Clément Zrounba, Mohab Abdalla, Paul Jiménez, Mauricio Gomes de Queiroz, Benoît Charbonnier, Fabio Pavanello, Ian O'Connor, Sébastien Le Beux. 1-6 [doi]
• Fe-GCN: A 3D FeFET Memory Based PIM Accelerator for Graph Convolutional NetworksHongtao Zhong, Yu Zhu, Longfei Luo, Taixin Li, Chen Wang, Yixin Xu, Tianyi Wang, Yao Yu, Vijaykrishnan Narayanan, Yongpan Liu, Liang Shi, Huazhong Yang, Xueqing Li. 1-6 [doi]
• Revisiting Trojan Insertion Techniques for Post-Silicon Trojan Detection EvaluationVedika Saravanan, Mohammad Walid Charrwi, Samah Mohamed Saeed. 1-6 [doi]
• Design Space Exploration for CNN Offloading to FPGAs at the EdgeGuilherme Korol, Michael Guilherme Jordan, Mateus Beck Rutzig, Jerónimo Castrillón, Antonio Carlos Schneider Beck. 1-6 [doi]
• LEX - A Cell Switching Arcs Extractor: A Simple SPICE-Input Interface for Electrical CharacterizationRodrigo N. Wuerdig, Vitor Hugo F. Maciel, Ricardo Reis 0001, Sergio Bampi. 1-6 [doi]