Abstract is missing.
- Application Specific DRAMs TodayBetty Prince. 7-13 [doi]
- A Multilevel DRAM with Hierarchical Bitlines and Serial SensingBruce F. Cockburn, Jesús Hernández Tapia, Duncan G. Elliott. 14-19 [doi]
- Cost Optimum Embedded DRAM Design by Yield AnalysisYouhei Zenda, Koji Nakamae, Hiromu Fujioka. 20 [doi]
- Systematic Memory Test Generation for DRAM Defects Causing Two Floating NodesZaid Al-Ars, A. J. van de Goor. 27-32 [doi]
- A Fault Primitive Based Analysis of Linked Faults in RAMsZaid Al-Ars, Said Hamdioui, A. J. van de Goor. 33 [doi]
- Output Timing Measurement Using an Idd MethodJörg E. Vollrath. 43-46 [doi]
- Reducing Test Time of Embedded SRAMsBaosheng Wang, Josh Yang, André Ivanov. 47-52 [doi]
- A Testability-Driven Optimizer and Wrapper Generator for Embedded MemoriesRei-Fu Huang, Li-Ming Denq, Cheng-Wen Wu, Jin-Fu Li. 53 [doi]
- ITRS Commodity Memory RoadmapRoger Barth. 61-63 [doi]
- Optimal Spare Utilization in Repairable and Reliable Memory CoresMinsu Choi, Nohpill Park, Fabrizio Lombardi, Yong-Bin Kim, Vincenzo Piuri. 64-71 [doi]
- Applying Defect-Based Test to Embedded Memories in a COT ModelRobert C. Aitken. 72 [doi]
- A 40ns Random Access Time Low Voltage 2Mbits EEPROM Memory for Embedded ApplicationsJean Michel Daga, Caroline Papaix, Emmanuel Racape, Marylene Combe, Vincent Sialelli, Jeanine Guichaoua. 81-85 [doi]
- An Electrical Simulation Model for the Chalcogenide Phase-Change Memory CellDaniel Salamon, Bruce F. Cockburn. 86 [doi]