Table of Contents

• FEM Modeling of Thermal Aspect of Dielectric Inserted Under Source & Drain of 5 nm NanosheetVivek Kumar, Jyoti Patel, Arnab Datta, Sudeb Dasgupta. 3-11 [doi]
• Differential Multi-bit Through Glass Vias for Three-Dimensional Integrated CircuitsAjay Kumar, Rohit Dhiman. 12-26 [doi]
• Design of a Low-Voltage Charge-Sensitive Preamplifier Interfaced with Piezoelectric Tactile Sensor for Tumour DetectionKingsuk Bag, Kislay Deep, Sharad Verma, Shashi Prabha Yadav, Manish Goswami, Kavindra Kandpal. 27-38 [doi]
• Design, Simulation and Optimization of Aluminum Nitride Based AccelerometerRahul Kumar Gupta, Sanjeev Kumar Manhas. 39-52 [doi]
• Low Loss Enabled Semi-superjunction 4H-SiC IGBT for High Voltage and Current ApplicationMahesh Vaidya, Alok Naugarhiya, Shrish Verma, Guru Prasad Mishra. 53-64 [doi]
• Implications of Field Plate HEMT Towards Power Performance at Microwave X - BandKhushwant Sehra, Jeffin Shibu, Meena Mishra, Mridula Gupta, Dipendra Singh Rawal, Manoj Saxena. 65-75 [doi]
• Investigation of Traps in AlGaN/GaN HEMT Epitaxial Structure Using Conductance MethodChanchal, Ajay Kumar Visvkarma, Hardhyan Sheoran, Amit Malik, Robert Laishram, Dipendra Singh Rawal, Manoj Saxena. 76-84 [doi]
• Unveiling the Impact of Interface Traps Induced on Negative Capacitance Nanosheet FET: A Reliability PerspectiveAniket Gupta, Govind Bajpai, Navjeet Bagga, Shashank Banchhor, Sudeb Dasgupta, Anand Bulusu, Nitanshu Chauhan. 85-96 [doi]
• Impact of Temperature on NDR Characteristics of a Negative Capacitance FinFET: Role of Landau Parameter (α)Rajeewa Kumar Jaisawal, Sunil Rathore, P. N. Kondekar, Navjeet Bagga. 97-106 [doi]
• i-MAX: Just-In-Time Wakeup of Maximally Gated Router for Power Efficient Multiple NoCNeelkamal, Sonal Yadav, Hemangee K. Kapoor. 107-117 [doi]
• Quantum Tunnelling and Themonic Emission, Transistor SimulationShivendra Yadav, Deepak Joshi, Sanjib Kalita, Tushita Singh. 118-125 [doi]
• Electro-Thermal Analysis of Vertically Stacked Gate All Around Nano-sheet TransistorArvind Bisht, Yogendra Pratap Pundir, Pankaj Kumar Pal. 126-136 [doi]
• Fabrication, Optimization and Testing of Photoconductively Tuned SAW Device Using CBD MethodRahul Sharma, Harshal B. Nemade. 139-149 [doi]
• High Resolution Temperature Sensor Signal Processing ASIC for Cryo-Cooler ElectronicsAnuj Srivastava, Nishant Kumar, Nihar Ranjan Mohapatra, Hari Shankar Gupta. 150-157 [doi]
• Low Power, Wideband SiGe HBT LNA Covering 57-64 GHz BandPuneet Singh, Saroj Mondal, Krishnan S. Rengarajan. 161-171 [doi]
• Four Differential Channels, Programmable Gain, Programmable Data Rate Delta Sigma ADCMohd Asim Saeed, Deep Sehgal, Surinder Singh. 172-184 [doi]
• Low Power Dual-Band Current Reuse-based LC-Voltage Controlled Oscillator with Shared Inductor for IoT ApplicationsAnshul Verma, Bishnu Prasad Das. 185-198 [doi]
• Aging Resilient and Energy Efficient Ring Oscillator for PUF DesignAnmol Verma, Shubhang Srivastava, Ambika Prasad Shah. 199-211 [doi]
• A GaN Based Reverse Recovery Time Limiter Circuit Integrated with a Low Noise AmplifierNeha Bajpai, Yogesh Singh Chauhan. 212-221 [doi]
• Novel Configuration of Multi-mode Universal Shadow Filter Employing a New Active BlockDivya Singh, Sajal K. Paul. 222-233 [doi]
• Highly Non-linear Feed-Forward Arbiter PUF Against Machine Learning AttacksAranya Gupta, Sanjeev Manhas, Bishnu Prasad Das. 234-248 [doi]
• An Online Testing Technique for the Detection of Control Nodes Displacement Faults (CNDF) in Reversible CircuitsBappaditya Mondal, Udit Narayana Kar, Chandan Bandyopadhyay, Debashri Roy, Hafizur Rahaman 0001. 249-261 [doi]
• An Approach Towards Analog In-Memory Computing for Energy-Efficient Adder in SRAM ArrayS. Kavitha, Santosh Kumar Vishvakarma, B. S. Reniwal. 262-274 [doi]
• MANA: Multi-Application Mapping onto Mesh Network-on-Chip using ANNJitesh Choudhary, Vishesh Bindal, Soumya J.. 277-291 [doi]
• Metastable SR Flip-Flop Based True Random Number Generator Using QCA TechnologyAbhishek Maurya, Ayush Singh, Syed Farah Naz, Ambika Prasad Shah. 292-304 [doi]
• Hardware Design of Two Stage Reference Free Adaptive Filter for ECG DenoisingPriyank H. Prajapati, Anand D. Darji. 305-319 [doi]
• A Reconfigurable Arbiter PUF Based on VGSOT MTJKunal Kranti Das, Aditya Japa, Deepika Gupta. 320-330 [doi]
• Pass Transistor XOR Gate Based Radiation Hardened RO-PUFSyed Farah Naz, Sajid Khan 0001, Ambika Prasad Shah. 331-344 [doi]
• QCA Technology Based 8-Bit TRNG Design for Cryptography ApplicationsPrateek Sinha, Aniket Sharma, Nilay Naharas, Syed Farah Naz, Ambika Prasad Shah. 345-357 [doi]
• Signal Integrity and Power Loss Analysis for Different Bump Structures in Cylindrical TSVShivangi Chandrakar, Kunal Kranti Das, Deepika Gupta, Manoj Kumar Majumder. 358-372 [doi]
• Reliability Aware Global Routing of Graphene Nanoribbon Based InterconnectSubrata Das, Debesh Kumar Das, Soumya Pandit. 373-386 [doi]
• Low Cost Hardware Design of ECC Scalar MultiplicationHariveer Inumarty, M. Mohamed Asan Basiri. 387-396 [doi]
• Scalable Construction of Formal Error Guaranteed LUT-Based Approximate Multipliers with Analytical Worst-Case Error BoundAnishetti Venkatesh, Chandan Kumar Jha, G. U. Vinod, Masahiro Fujita, Virendra Singh. 397-407 [doi]
• Design of a Programmable Delay Line with On-Chip Calibration to Achieve Immunity Against Process VariationsKanika Monga, Eesha Karnawat, Nitin Chaturvedi, S. Gurunarayanan 0001. 408-419 [doi]
• High Performance Ternary Full Adder in CNFET-Memristor Logic TechnologyPanasa Srikanth, B. Srinivasu. 420-434 [doi]
• Synthesis of LUT Based Approximating Adder Circuits with Formal Error GuaranteesPooja Choudhary, Lava Bhargava, Masahiro Fujita, Virendra Singh. 435-449 [doi]
• CAR: Community Aware Graph Reordering for Efficient Cache Utilization in Graph AnalyticsShubham Singhania, Neelam Sharma, Varun Venkitaraman, Chandan Kumar Jha. 453-467 [doi]
• Indigenous Fab-Lab Hybrid Device Integration for Phase Change Memory for In-Memory ComputingWasi Uddin, Ankit Bende, Avinash Singh, Tarun Malviya, Rohit Ranjan, Kumar Priyadarshi, Udayan Ganguly. 468-477 [doi]
• 2) Nanocomposite Bilayer Hybrid RRAMShalu Saini, Anil Lodhi, Anurag Dwivedi, Arpit Khandelwal, Shree Prakash Tiwari. 478-485 [doi]
• RTQCC-14T: Radiation Tolerant Quadruple Cross Coupled Robust SRAM Design for Radiation Prone EnvironmentsPramod Kumar Bharti, Joycee Mekie. 486-498 [doi]
• Disrupting Low-Write-Energy vs. Fast-Read Dilemma in RRAM to Enable L1 Instruction CacheAshwin Sanjay Lele, Srivatsava Jandhyala, Saurabh Gangurde, Virendra Singh, Sreenivas Subramoney, Udayan Ganguly. 499-512 [doi]
• Implementation and Analysis of Convolution Image Filtering with RISC-V Based ArchitectureM. K. Aparna Nair, Vishwas Vasuki Gautam, Abhishek Revinipati, J. Soumya. 515-526 [doi]
• Development of Distributed Controller for Electronic Beam Steering Using Indigenous Rad-Hard ASICRamesh Kumar, Ajay Kumar Singh, Chiragkumar Patel, S. Vinay Kumar, Himanshu N. Patel, B. Saravana Kumar. 527-539 [doi]
• Tile Serial Protocol (TSP) ASIC for Distributed Controllers of Space-Borne RADARChiragkumar B. Patel, Ganesh A. Mulay, Himanshu N. Patel, Pooja Dhankher. 540-550 [doi]
• A Deep Dive into CORDIC Architectures to Implement Trigonometric FunctionsNarnindi Ramani, Saroj Mondal. 551-561 [doi]
• Impact of Operand Ordering in Approximate Multiplication in Neural Network and Image Processing ApplicationsKailash Prasad, Jinay Dagli, Neel Shah, Mallikarjun Pidagannavar, Joycee Mekie. 562-572 [doi]
• An Overlap-and-Add Based Time Domain Acceleration of CNNs on FPGA-CPU SystemsRudresh Pratap Singh, Shreyam Kumar, Jai Gopal Pandey. 573-583 [doi]
• Low Cost Implementation of Deep Neural Network on HardwareGaurav Kumar, Anuj Kumar, Satyadev Ahlawat, Yamuna Prasad. 584-594 [doi]