VLSI-SOC: From Systems to Chips - IFIP TC 10/ WG 10.5 Twelfth International Conference on Very Large Scale Integration of System on Chip (VLSI-SoC 2003), December 1-3, 2003, Darmstadt, Germany - researchr publication

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Manfred Glesner, Ricardo Augusto da Luz Reis, Leandro Soares Indrusiak, Vincent John Mooney III, Hans Eveking, editors, VLSI-SOC: From Systems to Chips - IFIP TC 10/ WG 10.5 Twelfth International Conference on Very Large Scale Integration of System on Chip (VLSI-SoC 2003), December 1-3, 2003, Darmstadt, Germany. Volume 200 of IFIP, Springer, 2006. [doi]

Conference: vlsi2006

Abstract is missing.

Effect of Power Optimizations on Soft Error RateVijay Degalahal, Rajaraman Ramanarayanan, Narayanan Vijaykrishnan, Yuan Xie, Mary Jane Irwin. 1-20 [doi]

Dynamic Models for Substrate Coupling in Mixed-Mode SystemsJoão M. S. Silva, Luis Miguel Silveira. 21-37 [doi]

Hinoc: A Hierarchical Generic Approach for on-Chip Communication, Testing and Debugging of SoCsThomas Hollstein, Ralf Ludewig, Heiko Zimmer, Christoph Mager, Simon Hohenstern, Manfred Glesner. 39-54 [doi]

Automated Conversion of SystemC Fixed-Point Data TypesAxel G. Braun, Djones Lettnin, Joachim Gerlach, Wolfgang Rosenstiel. 55-72 [doi]

Exploration of Sequential Depth by Evolutionary AlgorithmsNicole Drechsler, Rolf Drechsler. 73-83 [doi]

Validation of Asynchronous Circuit Specifications Using IF/CADPDominique Borrione, Menouer Boubekeur, Laurent Mounier, Marc Renaudin, Antoine Siriani. 85-100 [doi]

On-Chip Property Verification Using Assertion ProcessorsJosé Augusto Miranda Nacif, Claudionor Nunes Coelho, Harry Foster, Flávio Miana de Paula, Edjard Mota, Márcia Roberta Falcão Mota, Antônio Otávio Fernandes. 101-117 [doi]

Run-Time FPGA Reconfiguration for Power-/Cost-Optimized Real-time SystemsJürgen Becker, Michael Hübner, Michael Ullmann. 119-132 [doi]

A Switched Opamp Based 10 Bits Integrated ADC for Ultra Low Power ApplicationsGiuseppe Bonfini, Andrea S. Brogna, Roberto Saletti, Cristian Garbossa, Luca Colombini, Maurizio Bacci, Stefania Chicca, Franco Bigongiari. 133-147 [doi]

Exploring the Capabilities of Reconfigurable Hardware for OFDM-Based WlansThilo Pionteck, Lukusa D. Kabulepa, Manfred Glesner. 149-164 [doi]

Software-Based Test for Nonprogrammable Cores in Bus-Based System-On-Chip ArchitecturesAlexandre M. Amory, Leandro A. Oliveira, Fernando Gehm Moraes. 165-179 [doi]

Optimizing SOC Test Resources Using Dual SequencesWei Zou, Chris C. N. Chu, Sudhakar M. Reddy, Irith Pomeranz. 181-196 [doi]

A Novel full Automatic Layout Generation Strategy for Static CMOS CircuitsCristiano Lazzari, Cristiano Viana Domingues, José Luís Güntzel, Ricardo Reis. 197-211 [doi]

Low Power Java Processor for Embedded ApplicationsAntonio Carlos Schneider Beck, Luigi Carro. 213-228 [doi]

Impact of Gate Leakage on Efficiency of Circuit Block Switch-Off SchemesStephan Henzler, Philip Teichmann, Markus Koban, Jörg Berthold, Georg Georgakos, Doris Schmitt-Landsiedel. 229-245 [doi]

Evaluation Methodology for Single Electron Encoded Threshold Logic GatesCasper Lageweg, Sorin Cotofana, Stamatis Vassiliadis. 247-262 [doi]

Asynchronous Integration of Coarse-Grained Reconfigurable XPP-Arrays Into Pipelined Risc Processor DatapathJürgen Becker, Alexander Thomas, Maik Scheer. 263-279 [doi]

Gray Encoded Arithmetic Operators Applied to FFT and FIR Dedicated DatapathsEduardo A. C. da Costa, José C. Monteiro, Sergio Bampi. 281-297 [doi]

Stuck-At-Fault Testability of SPP Three-Level Logic FormsValentina Ciriani, Anna Bernasconi, Rolf Drechsler. 299-313 [doi]

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