Alin Razafindraibe - researchr alias

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Viewing Publication 1 - 10 from 10

2008

Physical Design of FPGA Interconnect to Prevent Information LeakageSumanta Chaudhuri, Sylvain Guilley, Philippe Hoogvorst, Jean-Luc Danger, Taha Beyrouthy, Alin Razafindraibe, Laurent Fesquet, Marc Renaudin. arc 2008: 87-98 [doi]

2007

A Novel Asynchronous e-FPGA Architecture for Security ApplicationsTaha Beyrouthy, Alin Razafindraibe, Laurent Fesquet, Marc Renaudin, Sumanta Chaudhuri, Sylvain Guilley, Jean-Luc Danger, Philippe Hoogvorst. fpt 2007: 369-372 [doi]

A Reconfigurable Cell for a Multi-Style Asynchronous FPGAPhilippe Hoogvorst, Sylvain Guilley, Sumanta Chaudhuri, Alin Razafindraibe, Taha Beyrouthy, Laurent Fesquet. recosoc 2007: 15-22

Analysis and Improvement of Dual Rail Logic as a Countermeasure Against DPAAlin Razafindraibe, Michel Robert, Philippe Maurine. patmos 2007: 340-351 [doi]

A Model of DPA Syndrome and Its Application to the Identification of Leaking GatesAlin Razafindraibe, Philippe Maurine. patmos 2007: 394-403 [doi]

Improvement of dual rail logic as a countermeasure against DPAAlin Razafindraibe, Michel Robert, Philippe Maurine. vlsi 2007: 270-275 [doi]

2006

Security evaluation of dual rail logic against DPA attacksAlin Razafindraibe, Philippe Maurine, Michel Robert, Marc Renaudin. vlsi 2006: 181-186 [doi]

Formal Evaluation of the Robustness of Dual-Rail Logic Against DPA AttacksAlin Razafindraibe, Michel Robert, Philippe Maurine. patmos 2006: 634-644 [doi]

2005

A Method to Design Compact Dual-rail Asynchronous PrimitivesAlin Razafindraibe, Michel Robert, Marc Renaudin, Philippe Maurine. patmos 2005: 571-580 [doi]

Compact and Secured Primitives for the Design of Asynchronous CircuitsAlin Razafindraibe, Michel Robert, Philippe Maurine. jolpe, 1(1):20-26, 2005. [doi]

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