Cyril Chevalier - researchr alias

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Viewing Publication 1 - 8 from 8

2017

A Cross-Level Power Estimation Technique to Enhance High-Level Power Models QualityAlejandro Nocua, Arnaud Virazel, Alberto Bosio, Patrick Girard 0001, Cyril Chevalier. jolpe, 13(1):10-28, 2017. [doi]

HPET: An Efficient Hybrid Power Estimation Technique to Improve High-Level Power CharacterizationAlejandro Nocua, Arnaud Virazel, Alberto Bosio, Patrick Girard 0001, Cyril Chevalier. jcsc, 26(8):1-19, 2017. [doi]

2016

A hybrid power modeling approach to enhance high-level power modelsAlejandro Nocua, Arnaud Virazel, Alberto Bosio, Patrick Girard, Cyril Chevalier. ddecs 2016: 151-156 [doi]

A Hybrid Power Estimation Technique to improve IP power models qualityAlejandro Nocua, Arnaud Virazel, Alberto Bosio, Patrick Girard 0001, Cyril Chevalier. vlsi 2016: 1-6 [doi]

2015

A generic clock controller for low power systems: Experimentation on an AXI busChadi Al Khatib, Claire Aupetit, Cyril Chevalier, Chouki Aktouf, Gilles Sicard, Laurent Fesquet. vlsi 2015: 307-312 [doi]

2014

Distributed asynchronous controllers for clock management in low power systemsChadi Al Khatib, Claire Aupetit, Alejandro Chagoya, Cyril Chevalier, Gilles Sicard, Laurent Fesquet. icecsys 2014: 379-382 [doi]

1995

BIST hardware generator for mixed test schemeChristian Dufaza, H. Viallon, Cyril Chevalier. date 1995: 424-430 [doi]

1993

LFSROM an algorithm for automatic design synthesis of hardware test pattern generatorChristian Dufaza, Cyril Chevalier, Lew Fock Chong Lew Yan Voon. vts 1993: 208-214 [doi]

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