Hung Tien Bui - researchr alias

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Viewing Publication 1 - 15 from 15

2013

Design of low power 4-bit flash ADC based on standard cellsMarcel Siadjine Njinowa, Hung Tien Bui, François-Raymond Boyer. newcas 2013: 1-4 [doi]

2012

Pipelined FPGA design of the Goertzel algorithm for exon predictionHung Tien Bui. iscas 2012: 572-575 [doi]

2011

Rapid prototyping of the Goertzel algorithm for hardware acceleration of exon predictionMichel Voyer, Sylvain-Robert Rivard, Luc Morin, Hung Tien Bui. iscas 2011: 85-88 [doi]

2010

Peak-to-peak jitter reduction technique for the Free-Running Period Synthesizer (FRPS)Marcel Siadjine Njinowa, Hung Tien Bui, François R. Boyer. iscas 2010: 1312-1315 [doi]

Sensorless vector control of PMSG for variable speed wind energy applicationsJogendra Singh Thongam, Pierre Bouchard, Valentin Giurgiu, Hung Tien Bui, Mohand A. Ouhrouche. ccece 2010: 1-5 [doi]

2008

Design of an all-digital variable length ring oscillator (VLRO) for clock synthesisHung Tien Bui. iscas 2008: 3422-3425 [doi]

High speed CDR using a novel binary phase detector with probable-lock-detectionHung Tien Bui. icecsys 2008: 1006-1009 [doi]

Design of a High-Speed Differential Frequency-to-Voltage Converter and Its Application in a 5-GHz Frequency-Locked LoopHung Tien Bui, Yvon Savaria. tcas, 55-I(3):766-774, 2008. [doi]

2007

A Low-Complexity High-Speed Clock Generator for Dynamic Frequency Scaling of FPGA and Standard-Cell Based DesignsBill Pontikakis, Hung Tien Bui, François R. Boyer, Yvon Savaria. iscas 2007: 633-636 [doi]

2006

Dual-Path and Diode-Tracking Active Inductors for MCML GatesHung Tien Bui. ccece 2006: 1060-1063 [doi]

High speed differential pulse-width control loop based on frequency-to-voltage convertersHung Tien Bui, Yvon Savaria. glvlsi 2006: 53-56 [doi]

2005

A Generic Method for Embedded Measurement and Compensation of Process and Temperature Variations in SoCsHung Tien Bui, Yvon Savaria. iwsoc 2005: 557-562 [doi]

2004

10 GHz PLL Using Active Shunt-Peaked MCML Gates and Improved Frequency Acquisition XOR Phase Detector in 0.18 µm CMOSHung Tien Bui, Yvon Savaria. iwsoc 2004: 115-118 [doi]

Shunt-peaking in MCML gates and its application in the design of a 20 Gb/s half-rate phase detectorHung Tien Bui, Yvon Savaria. iscas 2004: 369-372

2001

Five new high-performance multiplexer-based 1-bit full adder cellsAbdulkarim Al-Sheraidah, Bassem Alhalabi, Hung Tien Bui. icecsys 2001: 807-810 [doi]

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