Kenji Toda - researchr alias

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2008

2007

FPGA-Based Intrusion Detection System for 10 Gigabit EthernetToshihiro Katashita, Yoshinori Yamaguchi, Atusi Maeda, Kenji Toda. ieicet, 90-D(12):1923-1931, 2007. [doi]

2006

2005

Dynamic Load Balancing Using Network Transferable ComputerMegumi Hisayuki, Shinji Inoue, Yoshiaki Kakuda, Kenji Toda, Kuniyasu Suzaki. icdcsw 2005: 51-57 [doi]

FPGA-Based Content Protection System for Embedded Consumer ElectronicsHiroyuki Yokoyama, Kenji Toda. rtcsa 2005: 502-507 [doi]

2003

Adaptable Load Balancing Using Network Transferable Computer Associated with Mobile IPMegumi Hisayuki, Shinji Inoue, Yoshiaki Kakuda, Kenji Toda, Kuniyasu Suzaki. icdcsw 2003: 8-13 [doi]

2000

A Flexible Scheduling for Automobile Control Using Imprecise Computation and Its Fundamental EvaluationFuminori Nakanishi, Shinnya Hiraike, Shinji Inoue, Yoshiaki Kakuda, Kenji Toda. iceccs 2000: 210-217 [doi]

1999

Real-world applications of analog and digital evolvable hardware Tetsuya Higuchi, Masaya Iwata, Didier Keymeulen, Hidenori Sakanashi, Masahiro Murakawa, Isamu Kajitani, Eiichi Takahashi, Kenji Toda, Mehrdad Salami, Nobuki Kajihara, Nobuyuki Otsu. tec, 3(3):220-235, 1999.

1998

Automation of Chamfering by an industrial Robot, for the Case of Machined Hole on a Cylindrical WorkpieceNaoki Asakawa, Kenji Toda, Yoshimi Takeuchi. icra 1998: 2452-2457

1997

CODA-R: a reconfigurable testbed for real-time parallel computationYoshinori Yamaguchi, Kenji Toda, Kenji Nishida, Eiichi Takahashi. rtcsa 1997: 252-259 [doi]

1995

Performance comparison of real-time architectures using simulationHeejo Lee, Kenji Toda, Jong Kim, Kenji Nishida, Eiichi Takahashi, Yoshinori Yamaguchi. rtcsa 1995: 150 [doi]

1994

A Priority Forwarding Router Chip for Real-Time Interconnection NetworksKenji Toda, Kenji Nishida, Eiichi Takahashi, Yoshinori Yamaguchi. rtss 1994: 63-73

The Execution Model and the Architecture for Real-Time Parallel SystemsYoshinori Yamaguchi, Kenji Toda, Kenji Nishida, Eiichi Takahashi. ifip11-9 1994: 177-182

1993

The Hardware Architecture of the CODA Real-Time Parallel ProcessorKenji Nishida, Kenji Toda, Toshio Shimada, Yoshinori Yamaguchi. parco 1994: 395-402

1992

Real-Time Parallel Architecture for Sensor FunsionToshio Shimada, Kenji Toda, Kenji Nishida. jpdc, 15(2):143-152, 1992.

A priority forwarding scheme for real-time multistage interconnection networksKenji Toda, Kenji Nishida, Shuichi Sakai, Toshio Shimada. rtss 1992: 208-217 [doi]

1991

Parallel Multi-Context Architecture with High-Speed Synchronization MechanismKenji Toda, Kenji Nishida, Yoshinobu Uchibori, Shuichi Sakai, Toshio Shimada. ipps 1991: 336-343

1989

The Gene Concept and its Implementation for a Dataflow Schemed Parallel ComputerKenji Toda, Yoshinobu Uchibori, Toshitsugu Yuba. parle 1989: 306-322

1986

DBCL: Data-Flow Computing Base Language with n-Value LogicJayantha A. Herath, Nobuo Saito, Kenji Toda, Yoshinori Yamaguchi, Toshitsugu Yuba. fjcc 1986: 353-361

1984

EM-3: A Lisp-Based Data-Driven MachineYoshinori Yamaguchi, Kenji Toda, Jayantha A. Herath, Toshitsugu Yuba. fgcs 1984: 524-532

1983

A Performance Evaluation of a Lisp-Based Data-Driven Machine (EM-3)Yoshinori Yamaguchi, Kenji Toda, Toshitsugu Yuba. isca 1983: 363-369