Taiga Takata - researchr alias

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2011

A robust algorithm for pessimistic analysis of logic masking effects in combinational circuitsTaiga Takata, Yusuke Matsunaga. iolts 2011: 246-251 [doi]

Multiple-bit-upset and single-bit-upset resilient 8T SRAM bitcell layout with divided wordline structureS. Yoshimoto, T. Amashita, D. Kozuwa, Taiga Takata, M. Yoshimura, Yusuke Matsunaga, H. Yasuura, H. Kawaguchi, M. Yoshimoto. iolts 2011: 151-156 [doi]

2010

A heuristic algorithm for LUT-based FPGA technology mapping using the lower bound for DAG covering problem (abstract only)Taiga Takata, Yusuke Matsunaga. fpga 2010: 289 [doi]

2009

Efficient Cut Enumeration Heuristics for Depth-Optimum Technology Mapping for LUT-Based FPGAsTaiga Takata, Yusuke Matsunaga. ieicet, 92-A(12):3268-3275, 2009. [doi]

An efficient cut enumeration for depth-optimum technology mapping for LUT-based FPGAsTaiga Takata, Yusuke Matsunaga. glvlsi 2009: 351-356 [doi]

2008

Area recovery under depth constraint by Cut Substitution for technology mapping for LUT-based FPGAsTaiga Takata, Yusuke Matsunaga. aspdac 2008: 144-147 [doi]

2006