Takashi Ohsawa - researchr alias

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Viewing Publication 1 - 14 from 14

2023

A Fully Analog Deep Neural Network Inference Accelerator with Pipeline Registers Based on Master-Slave Switched CapacitorsYaxin Mei, Takashi Ohsawa. ieicetc, 106(9):477-485, September 2023. [doi]

2022

A Low-Cost Training Method of ReRAM Inference Accelerator Chips for Binarized Neural Networks to Recover Accuracy Degradation due to Statistical VariabilitiesZian Chen, Takashi Ohsawa. ieicetc, 105-C(8):375-384, August 2022. [doi]

2021

Compact Model of Magnetic Tunnel Junctions for SPICE Simulation Based on Switching ProbabilityHaoyan Liu, Takashi Ohsawa. ieicetc, 104-C(3):121-127, 2021. [doi]

2020

Co-Design of Binary Processing in Memory ReRAM Array and DNN Model Optimization AlgorithmYue Guan, Takashi Ohsawa. ieicetc, 103-C(11):685-692, 2020. [doi]

Array Design of High-Density Emerging Memories Making Clamped Bit-Line Sense Amplifier Compatible with Dummy Cell Average Read SchemeZiyue Zhang, Takashi Ohsawa. ieicetc, 103-C(8):372-380, 2020. [doi]

2019

User- Friendly Compact Model of Magnetic Tunnel Junctions for Circuit Simulation Based on Switching ProbabilityHaoyan Liu, Takashi Ohsawa. vlsi-dat 2019: 1-4 [doi]

2018

A New Read Scheme for High-Density Emerging MemoriesTakashi Ohsawa. ieicet, 101-C(6):423-429, 2018. [doi]

2012

2011

Generation of Accurate Reference Current for Data Sensing in High-Density Memories by Averaging Multiple Pairs of Dummy CellsTakashi Ohsawa, Kosuke Hatsuda, Katsuyuki Fujita, Fumiyoshi Matsuoka, Tomoki Higashi. jssc, 46(9):2148-2157, 2011. [doi]

2006

Design of a 128-mb SOI DRAM using the floating body cell (FBC)Takashi Ohsawa, Katsuyuki Fujita, Kosuke Hatsuda, Tomoki Higashi, Tomoaki Shino, Yoshihiro Minami, Hiroomi Nakajima, Mutsuo Morikado, Kazumi Inoh, Takeshi Hamamoto, Shigeyoshi Watanabe, Shuso Fujii, Tohru Furuyama. jssc, 41(1):135-145, 2006. [doi]

2005

A 333MHz random cycle DRAM using the floating body cellKosuke Hatsuda, Katsuyuki Fujita, Takashi Ohsawa. cicc 2005: 259-262 [doi]

2002

Memory design using a one-transistor gain cell on SOITakashi Ohsawa, Katsuyuki Fujita, Tomoki Higashi, Yoshihisa Iwata, Takeshi Kajiyama, Yoshiaki Asao, Kazumasa Sunouchi. jssc, 37(11):1510-1522, 2002. [doi]

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