Abstract is missing.
- Technology Trends and Adaptive ComputingMichael J. Flynn, Albert A. Liddicoat. 1-5 [doi]
- Prototyping Framework for Reconfigurable ProcessorsSergej Sawitzki, Steffen Köhler, Rainer G. Spallek. 6-16 [doi]
- An Emulator for Exploring RaPiD Configurable Computing ArchitecturesChris Fisher, Kevin Rennie, Guanbin Xing, Stefan G. Berg, Kevin Bolding, John H. Naegle, Daniel Parshall, Dmitriy Portnov, Adnan Sulejmanpasic, Carl Ebeling. 17-26 [doi]
- A New Placement Method for Direct Mapping into LUT-Based FPGAsJoerg Abke, Erich Barke. 27-36 [doi]
- fGREP - Fast Generic Routing Demand Estimation for Placed FPGA CircuitsPariVallal Kannan, Shankar Balachandran, Dinesh Bhatia. 37-47 [doi]
- Macrocell Architectures for Product Term Embedded Memory ArraysErnie Lin, Steven J. E. Wilton. 48-58 [doi]
- Gigahertz Reconfigurable Computing Using SiGe HBT BiCMOS FPGAsBryan S. Goda, Russell P. Kraft, Steven R. Carlough, Thomas W. Krawczyk Jr., John F. McDonald. 59-69 [doi]
- Memory Synthesis for FPGA-Based Reconfigurable ComputersAmit Kasat, Iyad Ouaiss, Ranga Vemuri. 70-80 [doi]
- Implementing a Hidden Markov Model Speech Recognition System in Programmable LogicStephen J. Melnikoff, Steven F. Quigley, Martin J. Russell. 81-90 [doi]
- Implementation of (Normalised) RLS Lattice on VirtexFelix Albu, Jiri Kadlec, Christopher I. Softley, Rudolf Matousek, Antonin Hermanek, Nick Coleman, Anthony Fagan. 91-100 [doi]
- Accelerating Matrix Product on Reconfigurable Hardware for Signal ProcessingAbbes Amira, Ahmed Bouridane, Peter Milligan. 101-111 [doi]
- Static Profile-Driven Compilation for FPGAsSrihari Cadambi, Seth Copen Goldstein. 112-122 [doi]
- Synthesizing RTL Hardware from Java Byte CodesMichael J. Wirthlin, Brad L. Hutchings, Carl Worth. 123-132 [doi]
- PuMA++: From Behavioral Specification to Multi-FPGA-PrototypeKlaus Harbich, Erich Barke. 133-141 [doi]
- Secure Configuration of Field Programmable Gate ArraysTom Kean. 142-151 [doi]
- Single-Chip FPGA Implementation of the Advanced Encryption Standard AlgorithmMáire McLoone, John V. McCanny. 152-161 [doi]
- JBits:::TM::: Implementations of the Advanced Encryption Standard (Rijndael)Scott McMillan, Cameron Patterson. 162-171 [doi]
- Task-Parallel Programming of Reconfigurable SystemsMarkus Weinhardt, Wayne Luk. 172-181 [doi]
- Chip-Based Reconfigurable Task ManagementGordon J. Brebner, Oliver Diessel. 182-191 [doi]
- Configuration Caching and SwappingSuraj Sudhir, Suman Nath, Seth Copen Goldstein. 192-202 [doi]
- Multiple Stereo Matching Using an Extended ArchitectureMiguel Arias-Estrada, Juan M. Xicotencatl. 203-212 [doi]
- Implementation of a NURBS to Bézier Conversor with Constant LatencyPaula N. Mallón, Montserrat Bóo, Javier D. Bruguera. 213-222 [doi]
- Reconfigurable Frame-Grabber for Real-Time Automated Visual Inspection (RT-AVI) SystemsSergio A. Cuenca, Francisco Ibarra, Rafael Álvarez. 223-231 [doi]
- Processing Models for the Next Generation Network [Abstract]Jeff Lawrence. 232 [doi]
- Tightly Integrated Placement and Routing for FPGAsPariVallal Kannan, Dinesh Bhatia. 233-242 [doi]
- Gambit: A Tool for the Simultaneous Placement and Detailed Routing of Gate-ArraysJohn Karro, James P. Cohoon. 243-253 [doi]
- Reconfigurable Router Modules Using Network Protocol WrappersFlorian Braun, John W. Lockwood, Marcel Waldvogel. 254-263 [doi]
- Development of a Design Framework for Platform-Independent Networked Reconfiguration of Software and HardwareYajun Ha, Bingfeng Mei, Patrick Schaumont, Serge Vernalde, Rudy Lauwereins, Hugo De Man. 264-274 [doi]
- The MOLEN rho-mu-Coded ProcessorStamatis Vassiliadis, Stephan Wong, Sorin Cotofana. 275-285 [doi]
- Run-Time Optimized Reconfiguration Using Instruction ForecastingMarios Iliopoulos, Theodore Antonakopoulos. 286-295 [doi]
- CRISP: A Template for Reconfigurable Instruction Set ProcessorsPieter Op de Beeck, Francisco Barat, Murali Jayapala, Rudy Lauwereins. 296-305 [doi]
- Evaluation of an FPGA Implementation of the Discrete Element MethodBenjamin Carrión Schäfer, Steven F. Quigley, Andrew H. C. Chan. 306-314 [doi]
- Run-Time Performance Optimization of an FPGA-Based Deduction Engine for SAT SolversAndreas Dandalis, Viktor K. Prasanna, Bharani Thiruvengadam. 315-325 [doi]
- A Reconfigurable Embedded Input Device for Kinetically Challenged PersonsApostolos Dollas, Kyprianos Papademetriou, Nikolaos Aslanides, Tom Kean. 326-335 [doi]
- Bubble Partitioning for LUT-Based Sequential CircuitsFrank Wolz, Reiner Kolla. 336-345 [doi]
- Rapid Construction of Partial Configuration Datastreams from High-Level Constructs Using JBitsSatnam Singh, Philip James-Roxby. 346-356 [doi]
- Placing, Routing, and Editing Virtual FPGAsLoïc Lagadec, Dominique Lavenier, Erwan Fabiani, Bernard Pottier. 357-366 [doi]
- Virtex Implementation of Pipelined Adaptive LMS Predictor in Electronic Support Measures ReceiverLok-Kee Ting, Roger Woods, Colin Cowan. 367-376 [doi]
- A Music Synthesizer on FPGATakashi Saito, Tsutomu Maruyama, Tsutomu Hoshino, Saburo Hirano. 377-387 [doi]
- Motivation from a Full-Rate Specific Design to a DSP Core Approach for GSM VocodersShervin Sheidaei, Hamid Noori, Ahmad Akbari, Hossein Pedram. 388-397 [doi]
- Loop Tiling for Reconfigurable AcceleratorsSteven Derrien, Sanjay V. Rajopadhye. 398-408 [doi]
- The Systolic Ring: A Dynamically Reconfigurable Architecture for Embedded SystemsGilles Sassatelli, Lionel Torres, Jérôme Galy, Gaston Cambon, Camille Diou. 409-419 [doi]
- A n-Bit Reconfigurable Scalar QuantiserOswaldo Cadenas, Graham M. Megson. 420-429 [doi]
- Real Time Morphological Image Contrast Enhancement in Virtex FPGAJerzy Kasperek. 430-440 [doi]
- Demonstrating Real-Time JPEG Image Compression-Decompression Using Standard Component IP Cores on a Programmable Logic Based Platform for DSP and Image ProcessingAlbert Simpson, Jill Hunter, Moira Wylie, Yi Hu, David Mann. 441-450 [doi]
- Design and Implementation of an Accelerated Gabor Filter Bank Using Parallel HardwareNikolaus Voß, Bärbel Mertsching. 451-460 [doi]
- The Evolution of Programmable Logic: Past, Present, and Future Predictions [Abstract]Bill Carter. 461 [doi]
- Dynamically Reconfigurable CoresJohn MacBeth, Patrick Lysaght. 462-472 [doi]
- Reconfigurable Breakpoints for Co-debugTim Price, Cameron Patterson. 473-482 [doi]
- Using Design-Level Scan to Improve FPGA Design Observability and Controllability for Functional VerificationTimothy Wheeler, Paul Graham, Brent E. Nelson, Brad L. Hutchings. 483-492 [doi]
- FPGA-Based Fault Injection Techniques for Fast Evaluation of Fault Tolerance in VLSI CircuitsPierluigi Civera, Luca Macchiarulo, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante. 493-502 [doi]
- A Generic Library for Adaptive Computing EnvironmentsTilman Neumann, Andreas Koch. 503-512 [doi]
- Generative Development System for FPGA Processors with Active ComponentsStephan Rühl, Peter Dillinger, Stefan Hezel, Reinhard Männer. 513-522 [doi]
- Compilation Increasing the Scheduling Scope for Multi-memory-FPGA-Based Custom Computing MachinesJoão M. P. Cardoso, Horácio C. Neto. 523-533 [doi]
- System Level Tools for DSP in FPGAsJames Hwang, Brent Milne, Nabeel Shirazi, Jeffrey D. Stroomer. 534-543 [doi]
- Parameterized Function Evaluation for FPGAsOskar Mencer, Nicolas Boullis, Wayne Luk, Henry Styles. 544-554 [doi]
- Efficient Constant Coefficient Multiplication Using Advanced FPGA ArchitecturesMichael J. Wirthlin, Brian McMurtrey. 555-564 [doi]
- A Digit-Serial Structure for Reconfigurable MultipliersChakkapas Visavakul, Peter Y. K. Cheung, Wayne Luk. 565-573 [doi]
- FPGA Resource Reduction Through Truncated MultiplicationKent E. Wires, Michael J. Schulte, Don McCarley. 574-583 [doi]
- Efficient Mapping of Pre-synthesized IP-Cores onto Dynamically Reconfigurable Array ArchitecturesJürgen Becker, Nicolas Liebau, Thilo Pionteck, Manfred Glesner. 584-589 [doi]
- An FPGA-Based Syntactic Parser for Real-Life Almost Unrestricted Context-Free GrammarsCristian Ciressan, Eduardo Sanchez, Martin Rajman, Jean-Cédric Chappelier. 590-594 [doi]
- Hardware-Software Partitioning: A Reconfigurable and Evolutionary Computing ApproachJim Harkin, T. Martin McGinnity, Liam P. Maguire. 595-600 [doi]
- An Approach to Real-Time Visualization of PIV Method with FPGATsutomu Maruyama, Yoshiki Yamaguchi, Atsushi Kawase. 601-606 [doi]
- FPGA-Based Discrete Wavelet Transforms SystemMokhtar Nibouche, Ahmed Bouridane, Fionn Murtagh, Omar Nibouche. 607-612 [doi]
- X-MatchPRO: A ProASIC-Based 200 Mbytes/s Full-Duplex Lossless Data CompressorJose Luis Nunez, Claudia Feregrino, Simon Jones, Stephen Bateman. 613-617 [doi]
- Arithmetic Operation Oriented Reconfigurable Chip: RHWTsukasa Yamauchi, Shogo Nakaya, Takeshi Inuo, Nobuki Kajihara. 618-622 [doi]
- Initial Analysis of the Proteus ArchitectureMichael Dales. 623-627 [doi]
- Building Asynchronous Circuits with JBitsEric Keller. 628-632 [doi]
- Case Study of Integration of Reconfigurable Logic as a Coprocessor into a SCI-Cluster under RT-LinuxThomas Lehmann, Andreas Schreckenberg. 633-637 [doi]
- A Reconfigurable Approach to Packet FilteringRaymond Sinnappan, Scott Hazelhurst. 638-642 [doi]
- FPGA-Based Modelling Unit for High Speed Lossless Arithmetic CodingRiad Stefo, Jose Luis Nunez, Claudia Feregrino, Sudipta Mahapatra, Simon Jones. 643-647 [doi]
- A Data Re-use Based Compiler Optimization for FPGAsRam Subramanian, Santosh Pande. 648-652 [doi]
- Dijkstra s Shortest Path Routing Algorithm in Reconfigurable HardwareMatti Tommiska, Jorma Skyttä. 653-657 [doi]
- A System on Chip for Power Line Communications According to European Home Systems SpecificationsIsidoro Urriza, José I. García-Nicolás, Alfredo Sanz, Antonio Valdovinos. 658-662 [doi]