Abstract is missing.
- Technology research and development in Hong Kong: hype or realityPaul Y. S. Cheung. [doi]
- The hot decade of field programmable technologiesTsugio Makimoto. 3-6 [doi]
- FPGAs as meta-platforms for embedded systemsPatrick Lysaght. 7-12 [doi]
- Programmed solutions: the step beyond programmed logic [computer architecture]Michael J. Flynn. 13-16 [doi]
- The next big leap in reconfigurable systemsPaul Master. 17-22 [doi]
- Real-time packet editing using reconfigurable hardware for active networkingToshiaki Miyazaki, Takahiro Murooka, Noriyuki Takahashi, Masashi Hashimoto. 26-33 [doi]
- Implementation of an FPGA based accelerator for virtual private networksOcean Y. H. Cheung, Philip Heng Wai Leong. 34-41 [doi]
- Compiling run-time parametrisable designsArran Derbyshire, Wayne Luk. 44-51 [doi]
- Adaptive FIR filter architectures for run-time reconfigurable FPGAsTero Rissa, Riku Uusikartano, Jarkko Niittylahti. 52-59 [doi]
- A methodology for design of run-time reconfigurable systemsGareth Lee, George Milne. 60-67 [doi]
- Resource-aware run-time elaboration of behavioural FPGA specificationsUsama Malik, Keith So, Oliver Diessel. 68-75 [doi]
- Multiplier-less FIR digital filters using programmable sum-of-power-of-two (SOPOT) coefficientsK. S. Yeung, S. C. Chan. 78-84 [doi]
- FPGA-based system-level design framework based on the IRIS synthesis tool and System GeneratorYing Yi, Roger Woods. 85-92 [doi]
- Area and time efficient implementations of matrix multiplication on FPGAsJu-wook Jang, Seonil Choi, Viktor K. Prasanna. 93-100 [doi]
- A system level implementation of Rijndael on a memory-slot based FPGA cardDennis K. Y. Tong, Pui Sze Lo, Kin-Hong Lee, Philip Heng Wai Leong. 102-109 [doi]
- FPGA-based cloud detection for real-time onboard remote sensingJohn A. Williams, Anwar S. Dawood, Stephen J. Visser. 110-116 [doi]
- An FPGA-based processor for shogi mating problemsYohei Hori, Masashi Sonoyama, Tsutomu Maruyama. 117-124 [doi]
- Population based ant colony optimization on FPGAMichael Guntsch, Martin Middendorf, Bernd Scheuermann, Oliver Diessel, Hossam A. ElGindy, Hartmut Schmeck, Keith So. 125-132 [doi]
- Clustered programmable-reconfigurable processorsDerek B. Gottlieb, Jeffrey J. Cook, Joshua D. Walstrom, Steve Ferrera, Chi-Wei Wang, Nicholas P. Carter. 134-141 [doi]
- Implementing logic in FPGA memory arrays: heterogeneous memory architecturesSteven J. E. Wilton. 142-147 [doi]
- Optimising and adapting high-level hardware designsJosé Gabriel F. Coutinho, Wayne Luk. 150-157 [doi]
- Floating-point bitwidth analysis via automatic differentiationAltaf Abdul Gaffar, Oskar Mencer, Wayne Luk, Peter Y. K. Cheung, Nabeel Shirazi. 158-165 [doi]
- DRESC: a retargetable compiler for coarse-grained reconfigurable architecturesBingfeng Mei, Serge Vernalde, Diederik Verkest, Hugo De Man, Rudy Lauwereins. 166-173 [doi]
- HIDE: a logic based hardware intelligent description environmentS. Belkacemi, Khaled Benkrid, Danny Crookes. 174-180 [doi]
- Gigahertz SiGe BiCMOS FPGAs with new architectures and novel power management schemesKuan Zhou, Channakeshav, Michael Chu, Jong-Ru Guo, S.-C. Liu, Russell P. Kraft, Chao You, John F. McDonald. 182-188 [doi]
- Evolutionary analog circuit design on a programmable analog multiplexer arrayCristina Costa Santini, José F. M. do Amaral, Marco Aurélio Cavalcanti Pacheco, Marley B. R. Vellasco, Moisés H. Szwarcman. 189-196 [doi]
- An optically differential reconfigurable gate array and its power consumption estimationMinoru Watanabe, Fuminori Kobayashi. 197-202 [doi]
- A technology mapping algorithm for CPLD architecturesShih-Liang Chen, TingTing Hwang, C. L. Liu. 204-210 [doi]
- Power-aware technology mapping for LUT-based FPGAsJason Helge Anderson, Farid N. Najm. 211-218 [doi]
- Synthesizing datapath circuits for FPGAs with emphasis on area minimizationAndy Ye, Jonathan Rose, David M. Lewis. 219-226 [doi]
- The effect of cluster packing and node duplication control in delay driven clusteringMehrdad Eslami Dehkordi, Stephen Dean Brown. 227-233 [doi]
- Debug methodology for arithmetic circuits on FPGAsMasao Kubo, Masahiro Fujita. 236-242 [doi]
- Debug methods for hybrid CPU/FPGA systemsEric Roesler, Brent E. Nelson. 243-250 [doi]
- Scalable acceleration of inductive logic programsAndreas Fidjeland, Wayne Luk, Stephen Muggleton. 252-259 [doi]
- A fine-grained reconfigurable logic array based on double gate transistorsPaul Beckett. 260-267 [doi]
- A co-simulation study of adaptive EPIC computingStefan Valentin Gheorghita, Weng-Fai Wong, Tulika Mitra, Surendranath Talla. 268-275 [doi]
- System on programmable chip for real-time control implementationsDario L. Sancho-Pradel, Simon R. Jones, Roger Goodall. 276-283 [doi]
- A reconfigurable vision system for real-time applicationsCesar Torres-Huitzil, Selene Maya-Rueda, Miguel Arias-Estrada. 286-289 [doi]
- Lossless data compression programmable hardware for high-speed data networksJ. L. Nunez, S. Jones. 290-293 [doi]
- A multiplier-less FPGA core for image algebra neighbourhood operationsKhaled Benkrid. 294-297 [doi]
- Multi-hop routing of multi-terminal nets for evaluation of hybrid multi-FPGA boardsSushil Chandra Jain, Anshul Kumar, Shashi Kumar. 298-301 [doi]
- Serial-parallel tradeoff analysis of all-pairs shortest path algorithms in reconfigurable computingSui-Tung Mak, Kai-Pui Lam. 302-305 [doi]
- On-board satellite image compression using reconfigurable FPGAsAnwar S. Dawood, John A. Williams, Stephen J. Visser. 306-310 [doi]
- Efficient single-chip implementation of SHA-384 and SHA-512Máire McLoone, John V. McCanny. 311-314 [doi]
- An optimal PCM codec soft IP generator and its applicationGwo-Yang Wu, Liang-Bi Chen, Yuan-Long Jeang, Gwo-Jia Jong. 315-317 [doi]
- Efficient 4-input LUTs FPGA implementation of combinatorial multiplier over canonical base GF(16)Valeri F. Tomashau. 318-321 [doi]
- FPGA based real-time adaptive filtering for space applicationsStephen J. Visser, Anwar S. Dawood, John A. Williams. 322-326 [doi]
- Diagnosis of open defects in FPGA interconnectMehdi Baradaran Tahoori. 328-331 [doi]
- Testing for resistive open defects in FPGAsMehdi Baradaran Tahoori. 332-335 [doi]
- A novel three phase parallel genetic approach to routing for field programmable gate arraysAnnamalai Muthukaruppan, Sivaprakasam Suresh, V. Kamakoti. 336-339 [doi]
- Reconfigurable implementation of radiosity distribution computationJohn Y. H. Ko, Kam-Wing Ng. 340-343 [doi]
- Hardware Join Java: a high level language for reconfigurable hardware developmentJohn Hopf, G. Stewart Von Itzstein, David A. Kearney. 344-347 [doi]
- Image fusion for uninhabited airborne vehiclesMark Jasiunas, David A. Kearney, John Hopf, Grant B. Wigley. 348-351 [doi]
- Development framework for firewall processorsT. K. Lee, Sherif Yusuf, Wayne Luk, A. Sloman, Emil Lupu, Naranker Dulay. 352-355 [doi]
- Design and implementation of a novel architecture for symmetric FIR filters with boundary handling on Xilinx Virtex FPGAsAbdsamad Benkrid, Khaled Benkrid, Danny Crookes. 356-359 [doi]
- Enabling technologies for reconfigurable system-on-chipNeil W. Bergmann. 360-363 [doi]
- FPGA implementation of MFNN for image registrationD. C. Gharpure, M. S. Puranik. 364-367 [doi]
- An efficient architecture for an improved watershed algorithm and its FPGA implementationC. Rambabu, L. Chakrabarti, A. Mahanta. 370-373 [doi]
- The hardware implementation of a genetic algorithm model with FPGALei Tu, Ming-Cheng Zhu, Jing-Xia Wang. 374-377 [doi]
- Dynamic reconfiguration for the common key encryption using FPGATeruyoshi Yamaguchi, Tomonori Hashiyama, Shigeru Okuma. 378-381 [doi]
- Field modifiable architecture with FPGAs and its design methodologySatoshi Komatsu, Yoshihisa Kojima, Hiroshi Saito, Kenshu Seto, Masahiro Fujita. 382-385 [doi]
- The feasibility study of designing a FPGA multiplier-core on finite fieldC. H. Hsu, Trieu-Kien Truong, Ming-Haw Jing, W.-C. Wu, H. C. Wu. 386-389 [doi]
- The diversity study of AES on FPGA applicationMing-Haw Jing, C. H. Hsu, Trieu-Kien Truong, Yan-Haw Chen, Y. T. Chang. 390-393 [doi]
- Speedup analysis in simulation-emulation co-operationSeyed Ghassem Miremadi, Siavash Bayat Sarmadi, Ghazanfar Asadi. 394-398 [doi]
- Performing speech recognition on multiple parallel files using continuous hidden Markov models on an FPGAStephen J. Melnikoff, Steven F. Quigley, Martin J. Russell. 399-402 [doi]
- Evolution-based automated reconfiguration of field programmable analog devicesAdrian Stoica, Xin Guo, Ricardo Salem Zebulum, Michael I. Ferguson, Didier Keymeulen. 403-406 [doi]
- FPGA-based computation of free-form deformationsJun Jiang, Wayne Luk, Daniel Rueckert. 407-410 [doi]
- Incremental programming for reconfigurable enginesDong-U Lee, T. K. Lee, Wayne Luk, Peter Y. K. Cheung. 411-415 [doi]
- Delivering error detection capabilities into a field programmable device: the HORUS processor case studyFrancisco Rodríguez, José Carlos Campelo, Juan José Serrano. 418-421 [doi]
- Energy efficiency of FPGAs and programmable processors for matrix multiplicationRonald Scrofano, Seonil Choi, Viktor K. Prasanna. 422-425 [doi]
- Reconfigurable hardware control software using anonymous librariesChristian Hinkelbein, Reinhard Männer. 426-428 [doi]
- Logic synthesis of multi-output functions for PAL-based CPLDsDariusz Kania. 429-432 [doi]
- A method of implementing bit-serial LDI ladder filters in FPGAs using JBitsAlex Carreira, Trevor W. Fox, Laurence E. Turner. 433-436 [doi]
- PD-XML: extensible markup language for processor descriptionShay Ping Seng, Krishna V. Palem, Rodric M. Rabbah, Weng-Fai Wong, Wayne Luk, Peter Y. K. Cheung. 437-440 [doi]
- Sensitivity of FPGA power evaluationKara K. W. Poon, Steven J. E. Wilton. 441-442 [doi]
- Pattern recognition in the HADES spectrometer: an application of FPGA technology in nuclear and particle physicsIngo Fröhlich, Adrian Gabriel, Daniel Kirschner, Jörg Lehnert, Erik Lins, Markus Petri, Tiago Perez, Jim Ritman, Daniel Schäfer, Alberica Toia, Michael Traxler, Wolfgang Kuehn. 443-444 [doi]
- FPGA education and research activities in TaiwanYu-Tsang Chang, Yu-Te Chou, Wei-Chang Tsai, Jiann-Jenn Wang, Chen-Yi Lee. 445-448 [doi]
- Alternatives in FPGA-based SAD implementationsStephan Wong, Bastiaan Stougie, Sorin Cotofana. 449-452 [doi]
- Strassen's matrix multiplication for customisable processorsHenry M. D. Ip, James D. Low, Peter Y. K. Cheung, George A. Constantinides, Wayne Luk, Shay Ping Seng, Paul Metzgen. 453-456 [doi]