Abstract is missing.
- Faster minimization of linear wirelength for global placementCharles J. Alpert, Tony F. Chan, Dennis J.-H. Huang, Andrew B. Kahng, Igor L. Markov, Pep Mulet, Kenneth Yan. 4-11 [doi]
- Network flow based multi-way partitioning with area and pin constraintsHuiqun Liu, D. F. Wong. 12-17 [doi]
- Partitioning-based standard-cell global placement with an exact objectiveDennis J.-H. Huang, Andrew B. Kahng. 18-25 [doi]
- VLSI/PCB placement with obstacles based on sequence-pairHiroshi Murata, Kunihiro Fujiyoshi, Mineo Kaneko. 26-31 [doi]
- Timing driven placement in interaction with netlist transformationsGuenter Stenz, Bernhard M. Riess, Bernhard Rohfleisch, Frank M. Johannes. 36-41 [doi]
- Regular layout generation of logically optimized datapathsR. X. T. Nijssen, C. A. J. van Eijk. 42-47 [doi]
- Minimizing interconnect energy through integrated low-power placement and combinational logic synthesisGlenn Holt, Akhilesh Tyagi. 48-53 [doi]
- A simple and effective greedy multilayer router for MCMsYoung-Jun Cha, Chong S. Rim, Kazuo Nakajima. 67-72 [doi]
- Performance driven global routing for standard cell designJason Cong, Patrick H. Madden. 73-80 [doi]
- A min-cost flow based min-cost rectilinear Steiner distance-preserving tree constructionJun Dong Cho. 82-87 [doi]
- Efficient heuristics for the minimum shortest path Steiner arborescence problem with applications to VLSI physical designJason Cong, Andrew B. Kahng, Kwok-Shing Leung. 88-95 [doi]
- Provably good routing tree construction with multi-port terminalsC. Douglass Bateman, Christopher S. Helvig, Gabriel Robins, Alexander Zelikovsky. 96-102 [doi]
- A roadmap of CAD tool changes for sub-micron interconnect problemsLouis Scheffer. 104-109 [doi]
- C5M - a control logic layout synthesis system for high-performance microprocessorsJeffrey L. Burns, Jack A. Feldman. 110-115 [doi]
- A VLSI artwork legalization technique based on a new criterion of minimum layout perturbationFook-Luen Heng, Zhan Chen, Gustavo E. Téllez. 116-121 [doi]
- Concurrent transistor sizing and buffer insertion by considering cost-delay tradeoffsJuho Kim, Cyrus Bamji, Yanbin Jiang, Sachin S. Sapatnekar. 130-135 [doi]
- Towards a new benchmarking paradigm in EDA: analysis of equivalence class mutant circuit distributionsNevin Kapur, Debabrata Ghosh, Franc Brglez. 136-143 [doi]
- How good are slicing floorplans?Fung Yu Young, D. F. Wong. 144-149 [doi]
- Slicibility of rectangular graphs and floorplan optimizationParthasarathi Dasgupta, Susmita Sur-Kolay. 150-155 [doi]
- Power optimization for FPGA look-up tablesMichael J. Alexander. 156-162 [doi]
- A matrix synthesis approach to thermal placementChris C. N. Chu, D. F. Wong. 163-168 [doi]
- Preserving HDL synthesis hierarchy for cell placementYu-Wen Tsay, Wen-Jong Fang, Allen C.-H. Wu, Youn-Long Lin. 169-174 [doi]
- Minimization of chip size and power consumption of high-speed VLSI buffersD. Zhou, X. Y. Liu. 186-191 [doi]
- Closed form solution to simultaneous buffer insertion/sizing and wire sizingChris C. N. Chu, D. F. Wong. 192-197 [doi]
- Physical design: reminiscing and looking aheadErnest S. Kuh. 206 [doi]
- Physical design: mathematical models and methodsT. C. Hu. 207-210 [doi]
- The quarter micron challenge: intergrating physical and logic designRaul Camposano. 211 [doi]
- Chip hierarchical design system (CHDS): a foundation for timing-driven physical design into the 21st centuryR. G. Bushroe, S. DasGupta, A. Dengi, P. Fisher, S. Grout, G. Ledenbach, N. S. Nagaraj, R. Steele. 212-217 [doi]
- The future of logic synthesis and physical design in deep-submicron process geometriesKurt Keutzer, A. Richard Newton, Narendra V. Shenoy. 218-224 [doi]