Abstract is missing.
- SRAM Design Techniques for Sub-nano CMOS TechnologyJordan Lai. [doi]
- Program Committee [doi]
- High-Quality Memory TestMohamed Azimane. [doi]
- Organizing Committee [doi]
- New on-Chip DFT and ATE Features for Efficient Embedded Memory TestPeter Muhmenthaler. [doi]
- Future Prospective of Programmable Logic Non-volatile DeviceCharles Hsu. [doi]
- Non-volatile Semiconductor Memory Technology in Nanotech EraChih-Yuan Lu. [doi]
- Roadmap of the Flash MemoryRiichiro Shirota. [doi]
- Reviewers [doi]
- DRAM Industry TrendPei-Lin Pai. [doi]
- Foreword [doi]
- Fault-Pattern Oriented Defect Diagnosis for Flash MemoryMu-Hsien Hsu, Yu-Tsao Hsing, Jen-Chieh Yeh, Cheng-Wen Wu. 3-8 [doi]
- A March-Based Algorithm for Location and Full Diagnosis of All Unlinked Static FaultsT. A. Gyonjyan, Gurgen Harutunyan, Valery A. Vardanian. 9-14 [doi]
- Improved Representatives for Unrepairability Judging and Economic Repair Solutions of MemoriesHsing-Chung Liang, Le-Quen Tzeng. 15 [doi]
- A New 1T DRAM Cell With Enhanced Floating Body EfJyi-Tsong Lin, Mike Chang. 23-27 [doi]
- FlexiVia ROM Compiler Programmable on Different Via Layers Based on Top Metal AssignmentDing-Ming Kwai, Yung-Fa Chou, Meng-Fan Chang, Su-Meng Yang, Ding-Sheng Chen, Min-Chung Hsu, Yu-Zhen Liao, Shiao-Yi Lin, Yu-Ling Sung, Chia-Hsin Lee, Hsin-Kun Hsu. 28-33 [doi]
- Novel Memory Organization and Circuit Designs for Efficient Data Access in Applications of 3D Graphics and Multimedia CodingShen-Fu Hsiao, Yo-Chi Chen, Ming-Yu Tsai, Tze-Chong Cheng. 34-42 [doi]
- MRAM Write Error Categorization with QCKBYuui Shimizu, Hisanori Aikawa, Keiji Hosotani, Naoharu Shimomura, Tadashi Kai, Yoshihiro Ueda, Yoshiaki Asao, Yoshihisa Iwata, Kenji Tsuchida, Sumio Ikegawa. 43-48 [doi]
- DDR2 DRAM Output Timing OptimizationJörg E. Vollrath, Jürg Schwizer, Marcin Gnat, Ralf Schneider, Bret Johnson. 49-54 [doi]
- Dynamic Data Stability in SRAM Cells and Its Implications on Data Stability TestsMohammad Sharifkhani, Shah M. Jahinuzzaman, Manoj Sachdev. 55-64 [doi]
- SRAM Cell Current in Low Leakage DesignDing-Ming Kwai, Ching-Hua Hsiao, Chung-Ping Kuo, Chi-Hsien Chuang, Min-Chung Hsu, Yi-Chun Chen, Yu-Ling Sung, Hsien-Yu Pan, Chia-Hsin Lee, Meng-Fan Chang, Yung-Fa Chou. 65-70 [doi]
- On the Combined Impact of Soft and Medium Gate Oxide Breakdown and Process Variability on the Parametric Figures of SRAM componentsHua Wang, Miguel Miranda, Francky Catthoor, Wim Dehaene. 71-76 [doi]
- Detailed Comparisons of Program, Erase and Data Retention Characteristics between P+- and N+-Poly SONOS NAND Flash MemoryVictor Chao-Wei Kuo, Chih-Ming Chao, Chih-Kai Kang, Li-Wei Liu, Tzung-Bin Huang, Liang-Tai Kuo, Shi-Hsien Chen, Houng-Chi Wei, Hann-Ping Hwang, Saysamone Pittikoun. 77-79 [doi]
- Comparison of Electrical and Reliability Characteristics of Different Tunnel Oxides in SONOS Flash MemoryJia-Lin Wu, Hua-Ching Chien, Chien-Wei Liao, Cheng-Yen Wu, Chih-Yuan Lee, Houng-Chi Wei, Shih-Hsien Chen, Hann-Ping Hwang, Saysamone Pittikoun, Travis Cho, Chin-Hsing Kao. 80-84 [doi]