Wen-Kuan Yeh - researchr alias

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Viewing Publication 1 - 10 from 10

2020

Substrate Bias Effect on Dynamic Characteristics of a Monolithically Integrated GaN Half-BridgeWen Yang, Jiann-shiun Yuan, Balakrishnan Krishnan, An-Jye Tzou, Wen-Kuan Yeh. irps 2020: 1-5 [doi]

2019

Relationship of Channel and Surface Orientation to Mechanical and Electrical Stresses on N-Type FinFETsWen-Teng Chang, Shih-Wei Lin, Min-Cheng Chen, Wen-Kuan Yeh. ieicet, 102-C(6):429-434, 2019. [doi]

2016

Influence of fin number on hot-carrier injection stress induced degradation in bulk FinFETsWenqi Zhang, Tzuo-Li Wang, Yan-hua Huang, Tsu-Ting Cheng, Shih-Yao Chen, Yi-Ying Li, Chun-Hsiang Hsu, Chih-Jui Lai, Wen-Kuan Yeh, Yi-lin Yang. mr, 67:89-93, 2016. [doi]

2014

2013

The impact of interface/border defect on performance and reliability of high-k/metal-gate CMOSFETWen-Kuan Yeh, Po-Ying Chen, Kwang-Jow Gan, Jer-Chyi Wang, Chao Sung Lai. mr, 53(2):265-269, 2013. [doi]

2011

NBTI reliability on high-k metal-gate SiGe transistor and circuit performancesJiann-shiun Yuan, Wen-Kuan Yeh, Shuyu Chen, Chia-Wei Hsu. mr, 51(5):914-918, 2011. [doi]

2010

Improvement of TDDB reliability, characteristics of HfO::2:: high-k/metal gate MOSFET device with oxygen post deposition annealingChia-Wei Hsu, Yean-Kuen Fang, Wen-Kuan Yeh, Chun-Yu Chen, Yen-Ting Chiang, Feng-Renn Juang, Chien Ting Lin, Chieh-Ming Lai. mr, 50(5):618-621, 2010. [doi]

2008

Significantly improving sub-90 nm CMOSFET performances with notch-gate enhanced high tensile-stress contact etch stop layerChia-Wei Hsu, Yean-Kuen Fang, Wen-Kuan Yeh, Chien Ting Lin. mr, 48(11-12):1791-1794, 2008. [doi]

2007

The impacts of high tensile stress CESL and geometry design on device performance and reliability for 90 nm SOI nMOSFETsChieh-Ming Lai, Yean-Kuen Fang, Chien Ting Lin, Chia-Wei Hsu, Wen-Kuan Yeh. mr, 47(6):944-952, 2007. [doi]

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