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Viewing Publication 1 - 100 from 899

2019

2019 International Conference on ReConFigurable Computing and FPGAs, ReConFig 2019, Cancun, Mexico, December 9-11, 2019David Andrews 0001, René Cumplido, Claudia Feregrino, Marco Platzner, editors, IEEE, 2019. [doi]

Seiba: An FPGA Overlay-Based Approach to Rapid Application DevelopmentDavid Wilson 0004, Greg Stitt. reconfig 2019: 1-8 [doi]

An Open-Source Platform for Evaluation of Hardware Implementations of Lightweight Authenticated CiphersAbubakr Abdulgadir, William Diehl, Jens-Peter Kaps. reconfig 2019: 1-5 [doi]

Efficient FPGA-Based Reconfigurable Accelerators for SIMON Cryptographic Algorithm on Embedded PlatformsArkan Alkamil, Darshika G. Perera. reconfig 2019: 1-8 [doi]

Full hardware implementation of the Post-Quantum Public-Key Cryptography Scheme Round5Michal Andrzejczak, Farnoud Farahmand, Kris Gaj. reconfig 2019: 1-2 [doi]

Electronic System Level Power and Performance Analysis for Multi-Processor-System-on-ChipMuhammad Mudussir Ayub, Habibullah Ahmadzay, Josef Eckmüller, Franz Kreupl. reconfig 2019: 1-2 [doi]

High Throughput and Low Latency LZ4 Compressor on FPGATomás Benes, Matej Bartík, Pavel Kubalík. reconfig 2019: 1-5 [doi]

Approximate Adder Tree Synthesis for FPGAsSina Boroumand, Philip Brisk. reconfig 2019: 1-8 [doi]

Agile SMT-Based Mapping for CGRAs with Restricted Routing NetworksCaleb Donovick, Makai Mann, Clark W. Barrett, Pat Hanrahan. reconfig 2019: 1-8 [doi]

Decision-Tree Based Pixel Classification for Real-time Citrus Segmentation on FPGAIsmael-Antonio Dávila-Rodríguez, Marco Aurelio Nuño-Maganda, Yahir Hernandez-Mier, Said Polanco-Martagón. reconfig 2019: 1-8 [doi]

FPGA-Accelerated Decision Tree Classifier for Real-Time Supervision of Bluetooth SoCAbdelrahman Elkanishy, Derrick T. Rivera, Paul M. Furth, Abdel-Hameed A. Badawy, Youssef Aly, Christopher P. Michael. reconfig 2019: 1-5 [doi]

High-Speed Ring Oscillator based Sensors for Remote Side-Channel Attacks on FPGAsJoseph Gravellier, Jean-Max Dutertre, Yannick Teglia, Philippe Loubet-Moundi. reconfig 2019: 1-8 [doi]

BFLOAT MLP Training Accelerator for FPGAsAndrei Hagiescu, Martin Langhammer, Bogdan Pasca, Philip Colangelo, Jason Thong, Niayesh Ilkhani. reconfig 2019: 1-5 [doi]

A Catalog and In-Hardware Evaluation of Open-Source Drop-In Compatible RISC-V Softcore ProcessorsCarsten Heinz, Yannick Lavan, Jaco Hofmann, Andreas Koch 0001. reconfig 2019: 1-8 [doi]

RTRLib: A High-Level Modeling Tool for the Implementation of Dynamically Partial Reconfigurable System-on-ChipsRegina Marcela Ivo, Daniel M. Muñoz. reconfig 2019: 1-5 [doi]

On the Influence of the FPGA Compiler Optimization Options on the Success of the Horizontal AttackIevgen Kabin, Alejandro Sosa, Zoya Dyka, Dan Klann, Peter Langendörfer. reconfig 2019: 1-5 [doi]

An FPGA Accelerator for Embedded Microcontrollers Implementing a Ternarized Backpropagation AlgorithmTatsuya Kaneko, Hiroshi Momose, Tetsuya Asai. reconfig 2019: 1-8 [doi]

Efficient Utilization of DSPs and BRAMs Revisited: New AES-GCM Recipes on FPGAsElif Bilge Kavun, Nele Mentens, Jo Vliegen, Tolga Yalçin. reconfig 2019: 1-2 [doi]

A High Level Synthesis Approach for Application Specific DMA ControllersTomohiro Kida, Yuichi Kawamata, Yuichiro Shibata, Kentaro Sano. reconfig 2019: 1-2 [doi]

FPGA-based Accelerators of Fully Pipelined Modular Multipliers for Homomorphic EncryptionSunwoong Kim, Keewoo Lee, Wonhee Cho, Jung Hee Cheon, Rob A. Rutenbar. reconfig 2019: 1-8 [doi]

A Runtime Power-Aware Phase Predictor for CGRAsGuilherme Korol, Michael Guilherme Jordan, Raul Silveira Silva, Monica Magalhães Pereira, Marcelo Brandalero, Mateus Beck Rutzig, Antonio Carlos Schneider Beck. reconfig 2019: 1-8 [doi]

FPGA-based Accurate Pedestrian Detection with Thermal Camera for Surveillance SystemRyosuke Kuramochi, Masayuki Shimoda, Youki Sada, Shimpei Sato, Hiroki Nakahara. reconfig 2019: 1-5 [doi]

The Impact of Adopting Computational Storage in Heterogeneous Computing SystemsSen Ma, Shanyuan Gao. reconfig 2019: 1-8 [doi]

Design of a Flexible Schönhage-Strassen FFT Polynomial Multiplier with High- Level Synthesis to Accelerate HE in the CloudKevin Millar, Marcin Lukowiak, Stanislaw P. Radziszowski. reconfig 2019: 1-5 [doi]

TCD-NPE: A Re-configurable and Efficient Neural Processing Engine, Powered by Novel Temporal-Carry-deferring MACsAli Mirzaeian, Houman Homayoun, Avesta Sasan. reconfig 2019: 1-8 [doi]

A Library of FSM-based Floating-Point Arithmetic Functions on FPGAsAtiyehsadat Panahi, Keaten Stokke, David Andrews. reconfig 2019: 1-8 [doi]

Compiler-Based High-Level Synthesis of Application-Specific Processors on FPGAsPatrick Plagwitz, Franz-Josef Streit, Andreas Becher, Stefan Wildermann, Jürgen Teich. reconfig 2019: 1-8 [doi]

FPGA-ROS: Methodology to Augment the Robot Operating System with FPGA DesignsAriel Podlubne, Diana Göhringer. reconfig 2019: 1-5 [doi]

Efficient OpenCL Accelerators for Canny Edge Detection Algorithm on a CPU-FPGA PlatformSamah Rahamneh, Lina Sawalha. reconfig 2019: 1-5 [doi]

Volcan: System Integration of HLS and HMC on FPGAsAbhi D. Rajagopala, Ron Sass, Andrew G. Schmidt. reconfig 2019: 1-2 [doi]

UltraShare: FPGA-based Dynamic Accelerator Sharing and AllocationSiavash Rezaei, Eli Bozorgzadeh, Kanghee Kim. reconfig 2019: 1-5 [doi]

Isomorphic Subgraph-based Problem Reduction for Resource Minimal Modulo SchedulingPatrick Sittel, Nicolai Fiege, Martin Kumm, Peter Zipf. reconfig 2019: 1-8 [doi]

Implementation and Design Space Exploration of a Turbo Decoder in High-Level SynthesisWesley Stirk, Jeff Goeders. reconfig 2019: 1-5 [doi]

ROS-Enabled Hardware Framework for Experimental RoboticsBeck Strohmer, Anders Bøgild, Anders Stengaard Sørensen, Leon Bonde Larsen. reconfig 2019: 1-2 [doi]

Mixed-Signal Spin/Charge Reconfigurable Array for Energy-Aware Compressive Signal ProcessingAdrian Tatulian, Soheil Salehi, Ronald F. DeMara. reconfig 2019: 1-8 [doi]

iDocChip - A Configurable Hardware Architecture for Historical Document Image Processing: Text Line ExtractionMenbere Kina Tekleyohannes, Vladimir Rybalkin, Muhammad Mohsin Ghaffar, Norbert Wehn, Andreas Dengel 0001. reconfig 2019: 1-8 [doi]

TURTLE: A Low-Cost Fault Injection Platform for SRAM-based FPGAsCorbin Thurlow, Hayden Rowberry, Michael J. Wirthlin. reconfig 2019: 1-8 [doi]

Cycle-Accurate Debugging of Multi-clock Reconfigurable SystemsHabib ul Hasan Khan, Gökhan Akgün, Ariel Podlubne, Felix Wegener, Amir Moradi 0001, Diana Göhringer. reconfig 2019: 1-5 [doi]

Design of High Throughput FPGA-Based Testbed for Accelerating Error Characterization of LDPC CodesBurak Unal, Md Sahil Hassan, Joshua Mack, Nirmal Kumbhare, Ali Akoglu. reconfig 2019: 1-8 [doi]

Efficient FPGA Cost-Performance Space Exploration using Type-Driven Program TransformationsCristian Urlea, Wim Vanderbauwhede, Syed Waqar Nabi. reconfig 2019: 1-2 [doi]

Low Area Overhead Custom Buffering for FFTNils Voss, Stephen Girdlestone, Tobias Becker, Oskar Mencer, Wayne Luk, Georgi Gaydadjiev. reconfig 2019: 1-8 [doi]

Reconfigurable Real-Time Video Pipelines on SRAM-based FPGAsAndrew E. Wilson, Michael J. Wirthlin. reconfig 2019: 1-7 [doi]

Almost-Zero Logic Implementation of Troika Hash Function on Reconfigurable DevicesTalga Yalçin, Elif Bilge Kavun. reconfig 2019: 1-6 [doi]

2018

An Efficient FPGA-based Overlay Inference Architecture for Fully Connected DNNsAhmed M. Abdelsalam, Felix Boulet, Gabriel Demers, J. M. Pierre Langlois, Farida Cheriet. reconfig 2018: 1-6 [doi]

Dynamic tunable and reconfigurable hardware controller with EKF-based state reconstruction through FPGA-in the loopGökhan Akgün, Habib ul Hasan Khan, Mahmoud Ahmed Elshimy, Diana Göhringer. reconfig 2018: 1-8 [doi]

2018 International Conference on ReConFigurable Computing and FPGAs, ReConFig 2018, Cancun, Mexico, December 3-5, 2018David Andrews, René Cumplido, Claudia Feregrino, Dirk Stroobandt, editors, IEEE, 2018. [doi]

An FPGA-based Hardware Accelerator for Iris SegmentationJoe Avey, Phillip H. Jones, Joseph Zambreno. reconfig 2018: 1-8 [doi]

HW/SW Configurable LQG Controller using a Sequential Discrete Kalman FilterMatthew Cauwels, Joseph Zambreno, Phillip H. Jones. reconfig 2018: 1-8 [doi]

A Highly Parallel FPGA Implementation of Sparse Neural Network TrainingSourya Dey, Diandian Chen, Zongyang Li, Souvik Kundu, Kuan-Wen Huang, Keith M. Chugg, Peter A. Beerel. reconfig 2018: 1-4 [doi]

Flexible FPGA ECDSA Design with a Field Multiplier Inherently Resistant against HCCAZoya Dyka, Dan Kreiser, Ievgen Kabin, Peter Langendörfer. reconfig 2018: 1-6 [doi]

Towards a Generalized Reconfigurable Agent-Based Architecture: Stock Market Simulation AccelerationAlan Ehret, Mihailo Isakov, Michel A. Kinsy. reconfig 2018: 1-6 [doi]

High-Level Executable Models of Reactive Real-Time Systems with Logic-Labelled Finite-State Machines and FPGAsVladimir Estivill-Castro, René Hexel, Morgan McColl. reconfig 2018: 1-8 [doi]

Multi-Grain Reconfiguration for Advanced Adaptivity in Cyber-Physical SystemsTiziana Fanni, Alfonso Rodriguez, Carlo Sau, Leonardo Suriano, Francesca Palumbo, Luigi Raffo, Eduardo de la Torre. reconfig 2018: 1-8 [doi]

High-speed FPGA Implementation of the NIST Round 1 Rainbow Signature SchemeAhmed Ferozpuri, Kris Gaj. reconfig 2018: 1-8 [doi]

Design and Fabrication of Full Board Direct Liquid Cooling Heat Sink for Densely Packed FPGA Processing BoardsPaulina Fusiara, Gijs Schoonderbeek, Johan Pragt, Leon Hiemstra, Sjouke Kuindersma, Menno Schuil, Grant Hampson. reconfig 2018: 1-8 [doi]

Language Abstractions for Hardware-based Control-Flow Integrity MonitoringWilliam L. Harrison, Gerard Allwein. reconfig 2018: 1-6 [doi]

Exploring FPGA-specific Optimizations for Irregular OpenCL ApplicationsMohamed W. Hassan, Ahmed E. Helal, Peter M. Athanas, Wu-chun Feng, Yasser Y. Hanafy. reconfig 2018: 1-8 [doi]

AutoStreams: Fully Automatic parallelization of Legacy Embedded Applications with Soft-Core MPSoCsKris Heid, Christian Hochberger. reconfig 2018: 1-7 [doi]

Ant Colony Optimization based Module Footprint Selection and Placement for Lowering Power in Large FPGA DesignsKalindu Herath, Alok Prakash, Guiyuan Jiang, Thambipillai Srikanthan. reconfig 2018: 1-8 [doi]

Using Runtime Circuit Specialization to Accelerate Simulations of Reconfigurable ArchitecturesDillon Huff, Pat Hanrahan. reconfig 2018: 1-6 [doi]

A Coarse Grained-Reconfigurable Accelerator with energy efficient MTJ-based Non-volatile Flip-flopsTakeharu Ikezoe, Hideharu Amano, Junya Akaike, Kimiyoshi Usami, Masaru Kudo, Keizo Hiraga, Yusuke Shuto, Kojiro Yagami. reconfig 2018: 1-6 [doi]

A Scalable and Low Power DCNN for Multimodal Data ClassificationAli Jafari, Morteza Hosseini, Houman Homayoun, Tinoosh Mohsenin. reconfig 2018: 1-6 [doi]

Evaluating Floating-point Intensive Applications on OpenCL FPGA Platforms: A Case Study on the SimpleMOC KernelZheming Jin, Hal Finkel. reconfig 2018: 1-6 [doi]

FPGA Implementation of ECC: Low-Cost Countermeasure against Horizontal Bus and Address-Bit SCAIevgen Kabin, Dan Kreiser, Zoya Dyka, Peter Langendörfer. reconfig 2018: 1-7 [doi]

Full-HD Accelerated and Embedded Feature Detection Video System with 63fps using ORB for FREAKLester Kalms, Hassan Ibrahim, Diana Göhringer. reconfig 2018: 1-6 [doi]

An FPGA-oriented Graph Cut Algorithm for Accelerating Stereo VisionRyo Kamasaka, Yuichiro Shibata, Kiyoshi Oguri. reconfig 2018: 1-6 [doi]

Complex Multiply Accumulate Cells for the Square Kilometre Array CorrelatorsWilliam Kamp, Norbert Abel, Gianni Comoretto. reconfig 2018: 1-6 [doi]

A Coarse-Grained Reconfigurable Array for High-Performance Computing ApplicationsPhilipp S. Kasgen, Markus Weinhardt, Christian Hochberger. reconfig 2018: 1-4 [doi]

An Application Specific Framework for HLS-based FPGA Design of Articulated Robot Inverse KinematicsSafdar Mahmood, Pavel Shydlouski, Michael Hubner. reconfig 2018: 1-6 [doi]

Accelerating Key In-memory Database Functionality with FPGA TechnologyJohn McGlone, Paolo Palazzari, J. B. Leclere. reconfig 2018: 1-8 [doi]

A Composable Workflow for Productive Heterogeneous Computing on FPGAs via Whole-Program Analysis and TransformationPaul Sathre, Ahmed E. Helal, Wu-chun Feng. reconfig 2018: 1-8 [doi]

Post-Routing Analytical Wirelength Model for Homogeneous FPGA ArchitecturesArpit Soni, Yoon Kah Leow, Ali Akoglu. reconfig 2018: 1-8 [doi]

Model-Based Design Automation of Hardware/Software Co-Designs for Xilinx Zynq PSoCsFranz-Josef Streit, Martin Letras, Stefan Wildermann, Benjamin Hackenberg, Joachim Falk, Andreas Becher, Jürgen Teich. reconfig 2018: 1-8 [doi]

Throughput-Optimized Frequency Domain CNN with Fixed-Point Quantization on FPGAWeiyi Sun, Hanqing Zeng, Yi-Hua Edward Yang, Viktor K. Prasanna. reconfig 2018: 1-8 [doi]

FPGA-based TCP/IP Checksum Offloading Engine for 100 Gbps NetworksGustavo Sutter, Mario Ruiz, Sergio López-Buedo, Gustavo Alonso. reconfig 2018: 1-6 [doi]

FPGA-Based QBoost with Large-Scale Annealing Processor and Accelerated Hyperparameter SearchTakashi Takemoto, Normann Mertig, Masato Hayashi, Saki Susa-Tanaka, Hiroshi Teramoto, Atsuyoshi Nakamura, Ichigaku Takigawa, Shin-ichi Minato, Tamiki Komatsuzaki, Masanao Yamaoka. reconfig 2018: 1-8 [doi]

Experimental Power and Performance Evaluation of CAESAR Hardware FinalistsMichael Tempelmeier, Georg Sigl, Jens-Peter Kaps. reconfig 2018: 1-6 [doi]

System Services for Reconfigurable Hardware Acceleration in Mobile DevicesHsin-Yu Ting, Ardalan Amiri Sani, Eli Bozorgzadeh. reconfig 2018: 1-6 [doi]

LaKe: The Power of In-Network ComputingYuta Tokusashi, Hiroki Matsutani, Noa Zilberman. reconfig 2018: 1-8 [doi]

A small and adaptive coprocessor for information flow tracking in ARM SoCsMuhammad Abdul Wahab, Pascal Cotret, Mounir Nasr Allah, Guillaume Hiet, Arnab Kumar Biswas, Vianney Lapotre, Guy Gogniat. reconfig 2018: 1-8 [doi]

MBSS: A General Paradigm for Static Schedule for Nested Loops with Dynamic Loop Boundary on CGRAsShuai Xie, Zhongyuan Zhao, Weiguang Sheng, Qin Wang, Zhigang Mao. reconfig 2018: 1-8 [doi]

IMPRESS: Automated Tool for the Implementation of Highly Flexible Partial Reconfigurable Systems with Xilinx VivadoRafael Zamacola, Alberto García-Martínez, Javier Mora 0001, Andrés Otero, Eduardo de la Torre. reconfig 2018: 1-8 [doi]

Configuration Tampering of BRAM-based AES Implementations on FPGAsDaniel Ziener, Jutta Pirkl, Jürgen Teich. reconfig 2018: 1-7 [doi]

2017

International Conference on ReConFigurable Computing and FPGAs, ReConFig 2017, Cancun, Mexico, December 4-6, 2017IEEE, 2017. [doi]

H.264 video decoder implemented on FPGAs using 3×3 and 2×2 networks-on-chipIan J. Barge, Cristinel Ababei. reconfig 2017: 1-6 [doi]

Trusted display and input using screen overlaysAnthony Brandon, Michael Trimarchi. reconfig 2017: 1-6 [doi]

Fine-grained on-line power monitoring for soft microprocessor based system-on-chipYoung H. Cho, Siddharth S. Bhargav. reconfig 2017: 1-6 [doi]

Microchannels for thermal management in FPGAsGirish Deshpande, Dinesh K. Bhatia. reconfig 2017: 1-5 [doi]

Side-channel resistant soft core processor for lightweight block ciphersWilliam Diehl, Abubakr Abdulgadir, Jens-Peter Kaps, Kris Gaj. reconfig 2017: 1-8 [doi]

Minerva: Automated hardware optimization toolFarnoud Farahmand, Ahmed Ferozpuri, William Diehl, Kris Gaj. reconfig 2017: 1-8 [doi]

A Dynamically Reconfigurable Automata Processor OverlayRasha Karakchi, Lothrop O. Richards, Jason D. Bakos. reconfig 2017: 1-8 [doi]

Biologically inspired hierarchical structure for self-repairing FPGAsDavid C. Keezer, Jingchi Yang. reconfig 2017: 1-8 [doi]

Evaluation of CGRA architecture for real-time processing of biological signals on wearable devicesJoao Lopes, Diogo Sousa, João Canas Ferreira. reconfig 2017: 1-7 [doi]

Rapid circuit-specific inlining tuning for FPGA high-level synthesisDaniel H. Noronha, Jose P. Pinilla, Steven J. E. Wilton. reconfig 2017: 1-6 [doi]

Keynote 2 - FPGA-accelerated high-performance computing - Close to breakthrough or pipedream?Christian Plessi. reconfig 2017: 1 [doi]

An FPGA-in-the-loop approach for HDL motor controller verificationPaul Rogers, Rajesh Kavasseri, Scott C. Smith. reconfig 2017: 1-6 [doi]

Software defined network controller: A neat solution administration for reconfigurable multi-core NoCIbarra-Delgado Salvador, Sandoval-Arechiga Remberto, Maria Brox, Manuel A. Ortiz. reconfig 2017: 1-4 [doi]

Keynote 1 - Education is not learning facts, but training the mind to thinkJohn Watson. reconfig 2017: 1 [doi]

Evaluation of the CAESAR hardware API for lightweight implementationsPanasayya Yalla, Jens-Peter Kaps. reconfig 2017: 1-6 [doi]

A single-FPGA architecture for detecting heavy hitters in 100 Gbit/s ethernet linksJose Fernando Zazo, Sergio López-Buedo, Mario Ruiz, Gustavo Sutter. reconfig 2017: 1-6 [doi]

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