| 226 | -- | 0 | Takeshi Yamamura. Foreword |
| 227 | -- | 237 | Ryoichi Ishihara, Jin Zhang, Miki Trifunovic, Jaber Derakhshandeh, Negin Golshani, Daniel M. R. Tajari Mofrad, Tao Chen, Kees Beenakker, Tatsuya Shimoda. Single-Grain Si Thin-Film Transistors for Monolithic 3D-ICs and Flexible Electronics |
| 238 | -- | 244 | Kenichi Hatasako, Tetsuya Nitta, Masami Hane, Shigeto Maegawa. Past and Future Technology for Mixed Signal LSI |
| 245 | -- | 252 | Koji Kotani, Takumi Bando, Yuki Sasaki. A Photovoltaic-Assisted CMOS Rectifier for Synergistic Energy Harvesting from Ambient Radio Waves |
| 253 | -- | 263 | Jeong-Gun Lee, Myeong-Hoon Oh. Asynchronous Circuit Designs on an FPGA for Targeting a Power/Energy Efficient SoC |
| 264 | -- | 271 | Kumpei Yoshikawa, Kouji Ichikawa, Makoto Nagata. AC Power Supply Noise Simulation of CMOS Microprocessor with LSI Chip-Package-Board Integrated Model |
| 272 | -- | 279 | Daisuke Fujimoto, Noriyuki Miura, Makoto Nagata, Yu-ichi Hayashi, Naofumi Homma, Takafumi Aoki, Yohei Hori, Toshihiro Katashita, Kazuo Sakiyama, Thanh-Ha Le, Julien Bringer, Pirouz Bazargan-Sabet, Shivam Bhasin, Jean-Luc Danger. Power Noise Measurements of Cryptographic VLSI Circuits Regarding Side-Channel Information Leakage |
| 280 | -- | 288 | Shiho Hagiwara, Takanori Date, Kazuya Masu, Takashi Sato. Hypersphere Sampling for Accelerating High-Dimension and Low-Failure Probability Circuit-Yield Analysis |
| 289 | -- | 297 | Kenichi Ohhata. 1-GHz, 17.5-mW, 8-bit Subranging ADC Using Offset-Cancelling Charge-Steering Amplifier |
| 298 | -- | 307 | Sanroku Tsukamoto, Masaya Miyahara, Akira Matsuzawa. A 7-bit 1-GS/s Flash ADC with Background Calibration |
| 308 | -- | 315 | Rompei Sugawara, Hao San, Kazuyuki Aihara, Masao Hotta. Experimental Implementation of Non-binary Cyclic ADCs with Radix Value Estimation Algorithm |
| 316 | -- | 324 | Jeonghoon Han, Masaya Miyahara, Akira Matsuzawa. Injection Locked Charge-Pump PLL with a Replica of the Ring Oscillator |
| 325 | -- | 331 | SinNyoung Kim, Akira Tsuchiya, Hidetoshi Onodera. Radiation-Hardened PLL with a Switchable Dual Modular Redundancy Structure |
| 332 | -- | 341 | Yohei Nakata, Yuta Kimi, Shunsuke Okumura, Jinwook Jung, Takuya Sawada, Taku Toshikawa, Makoto Nagata, Hirofumi Nakano, Makoto Yabuuchi, Hidehiro Fujiwara, Koji Nii, Hiroyuki Kawai, Hiroshi Kawaguchi, Masahiko Yoshimoto. A 40-nm Resilient Cache Memory for Dynamic Variation Tolerance Delivering ×91 Failure Rate Improvement under 35% Supply Voltage Fluctuation |
| 342 | -- | 350 | Koh Johguchi, Toru Egami, Kousuke Miyaji, Ken Takeuchi. A Temperature Tracking Read Reference Current and Write Voltage Generator for Multi-Level Phase Change Memories |
| 351 | -- | 359 | Koh Johguchi, Kasuaki Yoshioka, Ken Takeuchi. NAND Phase Change Memory with Block Erase Architecture and Pass-Transistor Design Requirements for Write and Disturbance |
| 360 | -- | 368 | Takashi Miyamori, Hui Xu, Hiroyuki Usui, Soichiro Hosoda, Toru Sano, Kazumasa Yamamoto, Takeshi Kodaka, Nobuhiro Nonogaki, Nau Ozaki, Jun Tanabe. Architecture and Evaluation of Low Power Many-Core SoC with Two 32-Core Clusters |
| 369 | -- | 376 | Yoshihiro Tsunemi, Kazuhiro Ikeda, Hitoshi Kawaguchi. Analysis of Optical Output Characteristics in Waveguide Coupled HCG-VCSELs |
| 377 | -- | 385 | Daying Sun, Weifeng Sun, Qing Wang, Miao Yang, Shen Xu, Shengli Lu. Digital Controller for Single-Phase DCM Boost PFC Converter with High Power Factor over Wide Input Voltage and Load Range |
| 386 | -- | 391 | Ting Chen, Hengzhu Liu, Botao Zhang. CoDMA: Buffer Avoided Data Exchange in Distributed Memory Systems |