Journal: Integration

Volume 38, Issue 3

341 -- 352Sankar Barua, Joan Carletta, Kishore A. Kotteri, Amy E. Bell. An efficient architecture for lifting-based two-dimensional discrete wavelet transforms
353 -- 382Praveen Vellanki, Nilanjan Banerjee, Karam S. Chatha. Quality-of-service and error control techniques for mesh-based network-on-chip architectures
383 -- 398Zhiyuan Yan, Dilip V. Sarwate, Zhongzhi Liu. High-speed systolic architectures for finite field inversion
399 -- 415Roghoyeh Salmeh, Brent Maundy. Complete automatic ::::Q:::: tuning system on a chip
417 -- 437Hassan Hassan, Mohab Anis, Mohamed I. Elmasry. Design and optimization of MOS current mode logic for parameter variations
439 -- 449Yukiko Kubo, Hiroshi Miyashita, Yoji Kajitani, Kazuyuki Tateishi. Equidistance routing in high-speed VLSI layout design
451 -- 465Shalini Ghosh, F. Joel Ferguson. Detection probabilities of interconnect breaks: an analysis
467 -- 490Franco Fummi, Cristina Marconcini, Graziano Pravadelli. Logic-level mapping of high-level faults
491 -- 504Phillip Chin, Charles A. Zukowski, George Gristede, Stephen V. Kosonocky. Characterization of logic circuit techniques and optimization for high-leakage CMOS technologies
505 -- 513Davood Shahrjerdi, Bahman Hekmatshoar, Ali Khaki-Firooz, Ali Afzali-Kusha. Optimization of the V::T:: control method for low-power ultra-thin double-gate SOI logic circuits
515 -- 524Matteo Monchiero, Gianluca Palermo, Mariagiovanna Sami, Cristina Silvano, Vittorio Zaccaria, Roberto Zafalon. Low-power branch prediction techniques for VLIW architectures: a compiler-hints based approach
525 -- 540Jong-Ru Guo, Chao You, Kuan Zhou, Michael Chu, Peter F. Curran, Jiedong Diao, Bryan S. Goda, Russell P. Kraft, John F. McDonald. A 10 GHz 4: 1 MUX and 1: 4 DEMUX implemented by a Gigahertz SiGe FPGA for fast ADC
541 -- 548Ramprasad Ravichandran, Sung Kyu Lim, Michael T. Niemier. Automatic cell placement for quantum-dot cellular automata