Journal: Integration

Volume 38, Issue 4

549 -- 570Wen-Tsong Shiue. Novel state minimization and state assignment in finite state machine design for low-power portable devices
571 -- 578Yeun-Renn Ting, Erl-Huei Lu, Ya-Cheng Lu. Ringed bit-parallel systolic multipliers over a class of fields GF(2:::::::m:::::::)
579 -- 596Ashok K. Srivastava, Srinivas Rao Aluri, Anand Kumar Chamakura. A simple built-in current sensor for IDDQ testing of CMOS data converters
597 -- 613Arda Yurdakul. Multiplierless implementation of 2-D FIR filters

Volume 38, Issue 3

341 -- 352Sankar Barua, Joan Carletta, Kishore A. Kotteri, Amy E. Bell. An efficient architecture for lifting-based two-dimensional discrete wavelet transforms
353 -- 382Praveen Vellanki, Nilanjan Banerjee, Karam S. Chatha. Quality-of-service and error control techniques for mesh-based network-on-chip architectures
383 -- 398Zhiyuan Yan, Dilip V. Sarwate, Zhongzhi Liu. High-speed systolic architectures for finite field inversion
399 -- 415Roghoyeh Salmeh, Brent Maundy. Complete automatic ::::Q:::: tuning system on a chip
417 -- 437Hassan Hassan, Mohab Anis, Mohamed I. Elmasry. Design and optimization of MOS current mode logic for parameter variations
439 -- 449Yukiko Kubo, Hiroshi Miyashita, Yoji Kajitani, Kazuyuki Tateishi. Equidistance routing in high-speed VLSI layout design
451 -- 465Shalini Ghosh, F. Joel Ferguson. Detection probabilities of interconnect breaks: an analysis
467 -- 490Franco Fummi, Cristina Marconcini, Graziano Pravadelli. Logic-level mapping of high-level faults
491 -- 504Phillip Chin, Charles A. Zukowski, George Gristede, Stephen V. Kosonocky. Characterization of logic circuit techniques and optimization for high-leakage CMOS technologies
505 -- 513Davood Shahrjerdi, Bahman Hekmatshoar, Ali Khaki-Firooz, Ali Afzali-Kusha. Optimization of the V::T:: control method for low-power ultra-thin double-gate SOI logic circuits
515 -- 524Matteo Monchiero, Gianluca Palermo, Mariagiovanna Sami, Cristina Silvano, Vittorio Zaccaria, Roberto Zafalon. Low-power branch prediction techniques for VLIW architectures: a compiler-hints based approach
525 -- 540Jong-Ru Guo, Chao You, Kuan Zhou, Michael Chu, Peter F. Curran, Jiedong Diao, Bryan S. Goda, Russell P. Kraft, John F. McDonald. A 10 GHz 4: 1 MUX and 1: 4 DEMUX implemented by a Gigahertz SiGe FPGA for fast ADC
541 -- 548Ramprasad Ravichandran, Sung Kyu Lim, Michael T. Niemier. Automatic cell placement for quantum-dot cellular automata

Volume 38, Issue 2

131 -- 183Matthias Gries. Methods for evaluating and covering the design space during early design development
185 -- 203Martin Margala, Hongfan Wang. New approach to design for reusability of arithmetic cores in systems-on-chip
205 -- 225Magdy A. El-Moursy, Eby G. Friedman. Optimum wire sizing of ::::RLC:::: interconnect with repeaters
227 -- 243Falk Roewer, Ulrich Kleine, Klaus-Eberhard Salzwedel, Felix Mednikov, Chhrisitan Pfaffinger, Martin Sellen. A programmable inductive position sensor interface circuit
245 -- 265Guang-Ming Wu, Mango Chia-Tso Chao, Yao-Wen Chang. A clustering- and probability-based approach for time-multiplexed FPGA partitioning
267 -- 281Soumen Maity, Amiya Nayak, Bimal K. Roy. On characterization of catastrophic faults in two-dimensional VLSI arrays
283 -- 298Abdoul Rjoub, Odysseas G. Koufopavlou. Multithreshold voltage low-swing/low-voltage techniques in logic gates
299 -- 307Ali Ziya Alkar, Remziye Sönmez. A hardware version of the RSA using the Montgomery s algorithm with systolic arrays
309 -- 339Robertas Damasevicius, Vytautas Stuikys. Application of the object-oriented principles for hardware and embedded system design

Volume 38, Issue 1

1 -- 2Luca Benini. Guest Editorial
3 -- 17Dinesh Pamunuwa, Johnny Öberg, Li-Rong Zheng, Mikael Millberg, Axel Jantsch, Hannu Tenhunen. A study on the implementation of 2-D mesh-based networks-on-chip in the nanometre regime
19 -- 42Evgeny Bolotin, Israel Cidon, Ran Ginosar, Avinoam Kolodny. Cost considerations in network on chip
43 -- 67Pasi Liljeberg, Juha Plosila, Jouni Isoaho. Self-timed communication platform for implementing high-performance systems-on-chip
69 -- 93Fernando Gehm Moraes, Ney Calazans, Aline Mello, Leandro Möller, Luciano Ost. HERMES: an infrastructure for low area overhead packet-switching networks on chip
95 -- 105David A. Sigüenza-Tortosa, Tapani Ahonen, Jari Nurmi. Issues in the development of a practical NoC: the Proteo concept
107 -- 130Théodore Marescaux, Vincent Nollet, Jean-Yves Mignolet, Andrei Bartic, W. Moffat, Prabhat Avasare, Paul Coene, Diederik Verkest, Serge Vernalde, Rudy Lauwereins. Run-time support for heterogeneous multitasking on reconfigurable SoCs