Journal: JETC

Volume 12, Issue 4

31 -- 0Hoda Aghaei Khouzani, Yuan Xue, Chengmo Yang. Fully Exploiting PCM Write Capacity Within Near Zero Cost Through Segment-Based Page Allocation
32 -- 0Christophe Layer, Laurent Becker, Kotb Jabeur, Sylvain Claireux, Bernard Dieny, Guillaume Prenat, Gregory di Pendina, Stephane Gros, Pierre Paoli, Virgile Javerliac, Fabrice Bernard-Granger, Loïc Decloedt. Reducing System Power Consumption Using Check-Pointing on Nonvolatile Embedded Magnetic Random Access Memories
33 -- 0Chengwen Wu, Guangyan Zhang, Keqin Li. Rethinking Computer Architectures and Software Systems for Phase-Change Memory
34 -- 0Arighna Deb, Debesh K. Das, Hafizur Rahaman, Robert Wille, Rolf Drechsler, Bhargab B. Bhattacharya. Reversible Synthesis of Symmetric Functions with a Simple Regular Structure and Easy Testability
35 -- 0Qian Wang, Yongtae Kim, Peng Li. Neuromorphic Processors with Memristive Synapses: Synaptic Interface and Architectural Exploration
36 -- 0Kalyan Biswas, Angsuman Sarkar, Chandan Kumar Sarkar. Impact of Fin Width Scaling on RF/Analog Performance of Junctionless Accumulation-Mode Bulk FinFET
37 -- 0Yi-Hang Chen, Jian-Yu Chen, Juinn-Dar Huang. Area Minimization Synthesis for Reconfigurable Single-Electron Transistor Arrays with Fabrication Constraints
38 -- 0Moon Seok Kim, William Cane-Wissing, Xueqing Li, Jack Sampson, Suman Datta, Sumeet Kumar Gupta, Vijaykrishnan Narayanan. Comparative Area and Parasitics Analysis in FinFET and Heterojunction Vertical TFET Standard Cells
39 -- 0Muhammad Ahsan, Rodney Van Meter, Jungsang Kim. Designing a Million-Qubit Quantum Computer Using a Resource Performance Simulator
40 -- 0Mona Arabzadeh, Mahboobeh Houshmand, Mehdi Sedighi, Morteza Saheb Zamani. Quantum-Logic Synthesis of Hermitian Gates
41 -- 0Mathias Soeken, Robert Wille, Oliver Keszocze, D. Michael Miller, Rolf Drechsler. Embedding of Large Boolean Functions for Reversible Logic
42 -- 0Aoxiang Tang, Xun Gao, Lung-Yen Chen, Niraj K. Jha. Delay/Power Modeling and Optimization of FinFET Circuit Modules under PVT Variations: Observing the Trends between the 22nm and 14nm Technology Nodes
43 -- 0Sourindra M. Chaudhuri, Niraj K. Jha. Ultra-Low-Leakage and High-Performance Logic Circuit Design Using Multiparameter Asymmetric FinFETs
44 -- 0Anja von Beuningen, Luca Ramini, Davide Bertozzi, Ulf Schlichtmann. PROTON+: A Placement and Routing Tool for 3D Optical Networks-on-Chip with a Single Optical Layer
45 -- 0Abbas Dehghani 0002, Kamal Jamshidi. A Novel Approach to Optimize Fault-Tolerant Hybrid Wireless Network-on-Chip Architectures
46 -- 0Sparsh Mittal. A Survey of Architectural Techniques for Near-Threshold Computing

Volume 12, Issue 3

20 -- 0Yiyu Shi, Takashi Sato. Introduction to: Special Issue on Cross-Layer System Design
21 -- 0Vivek K. De, Andrew B. Kahng, Tanay Karnik, Bao Liu, Milad Maleki, Lu Wang. Application-Specific Cross-Layer Optimization Based on Predictive Variable-Latency VLSI Design
22 -- 0Milan Patnaik, Chidhambaranathan Rajamanikkam, Chirag Garg, Arnab Roy, V. R. Devanathan, Shankar Balachandran, V. Kamakoti. ProWATCh: A Proactive Cross-Layer Workload-Aware Temperature Management Framework for Low-Power Chip Multi-Processors
23 -- 0Chenyuan Zhao, Bryant T. Wysocki, Yifang Liu, Clare Thiem, Nathan R. McDonald, Yang Yi. Spike-Time-Dependent Encoding for Neuromorphic Processors
24 -- 0Martin Barke, Ulf Schlichtmann. A Cross-Layer Approach to Measure the Robustness of Integrated Circuits
25 -- 0Cheng Zhuo, Houle Gan, Wei-Kai Shih, Alaeddin A. Aydiner. A Cross-Layer Approach for Early-Stage Power Grid Design and Optimization
26 -- 0Jinho Lee, Kyungsu Kang, Kiyoung Choi. REDELF: An Energy-Efficient Deadlock-Free Routing for 3D NoCs with Partial Vertical Connections
27 -- 0Davide Zoni, William Fornaciari. Modeling DVFS and Power-Gating Actuators for Cycle-Accurate NoC-Based Simulators
28 -- 0Xianmin Chen, Niraj K. Jha. gem5-PVT: A Framework for FinFET System Simulation under PVT Variations
29 -- 0Tayebeh Bahreini, Naser MohammadZadeh. An MINLP Model for Scheduling and Placement of Quantum Circuits with a Heuristic Solution Approach
30 -- 0Mostafizur Rahman, Santosh Khasanvis, Csaba Andras Moritz. Nanowire Volatile RAM as an Alternative to SRAM

Volume 12, Issue 2

11 -- 0Aida Todri-Sanial, Sanjukta Bhanja. Guest Editorial: Special Issue on Advances in Design of Ultra-Low Power Circuits and Systems in Emerging Technologies
12 -- 0Pierre-Emmanuel Gaillardon, Edith Beigné, Suzanne Lesecq, Giovanni De Micheli. A Survey on Low-Power Techniques with Emerging Technologies: From Devices to Systems
13 -- 0Can Sitik, Emre Salman, Leo Filippini, Sung-Jun Yoon, Baris Taskin. FinFET-Based Low-Swing Clocking
14 -- 0Tiansheng Zhang, Jie Meng, Ayse Kivilcim Coskun. Dynamic Cache Pooling in 3D Multicore Processors
15 -- 0Santosh Khasanvis, K. M. Masum Habib, Mostafizur Rahman, Roger Lake, Csaba Andras Moritz. Low-Power Heterogeneous Graphene Nanoribbon-CMOS Multistate Volatile Memory Circuit
16 -- 0Wang Kang, Yue Zhang, Zhaohao Wang, Jacques-Olivier Klein, Claude Chappert, Dafine Ravelosona, Gefei Wang, Youguang Zhang, Weisheng Zhao. Spintronics: Emerging Ultra-Low-Power Circuits and Systems beyond MOS Technology
17 -- 0Mostafa Rahimi Azghadi, Saber Moradi, Daniel Bernhard Fasnacht, Mehmet Sirin Ozdas, Giacomo Indiveri. Programmable Spike-Timing-Dependent Plasticity Learning Circuits in Neuromorphic VLSI Architectures
18 -- 0Mariagrazia Graziano, Azzurra Pulimeno, Ruiyu Wang, Xiang Wei, Massimo Ruo Roch, Gianluca Piccinini. Process Variability and Electrostatic Analysis of Molecular QCA
19 -- 0Trong Nhan Le, Alain Pegatoquet, Olivier Berder, Olivier Sentieys, Arnaud Carer. Energy-Neutral Design Framework for Supercapacitor-Based Autonomous Wireless Sensor Networks

Volume 12, Issue 1

1 -- 0Jun Pang, Christopher Dwyer, Alvin R. Lebeck. mNoC: Large Nanophotonic Network-on-Chip Crossbars with Molecular Scale Devices
2 -- 0Nahid M. Hossain, Masud H. Chowdhury. Multilayer Graphene Nanoribbon and Carbon Nanotube Based Floating Gate Transistor for Nonvolatile Flash Memory
3 -- 0Amirali Ghofrani, Miguel Angel Lastras-Montaño, Siddharth Gaba, Melika Payvand, Wei Lu, Luke Theogarajan, Kwang-Ting Cheng. A Low-Power Variation-Aware Adaptive Write Scheme for Access-Transistor-Free Memristive Memory
4 -- 0Rangharajan Venkatesan, Mrigank Sharad, Kaushik Roy, Anand Raghunathan. Energy-Efficient All-Spin Cache Hierarchy Using Shift-Based Writes and Multilevel Storage
5 -- 0Kyu Ho Park, Woomin Hwang, Hyunchul Seok, Chulmin Kim, Dong-Jae Shin, Dong Jin Kim, Min Kyu Maeng, Seong-Min Kim. MN-MATE: Elastic Resource Management of Manycores and a Hybrid Memory Hierarchy for a Cloud Node
6 -- 0Jue Wang, Yuan Xie 0001. A Write-Aware STTRAM-Based Register File Architecture for GPGPU
7 -- 0Aldo Romani, Matteo Filippi, Michele Dini, Marco Tartagni. A Sub-μ A Stand-By Current Synchronous Electric Charge Extractor for Piezoelectric Energy Harvesting
8 -- 0Hrishikesh Jayakumar, Arnab Raha, Woo Suk Lee, Vijay Raghunathan. QuickRecall: A HW/SW Approach for Computing across Power Cycles in Transiently Powered Computers
9 -- 0Chia-Hung Chien, Rodney Van Meter, Sy-Yen Kuo. Fault-Tolerant Operations for Universal Blind Quantum Computation
10 -- 0Ching-Hwa Cheng. SCKVdd: A Scalable Clock-Controlled Self-Stabilized Voltage Technique for Low Power CMOS Digital Circuits