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Journal: IEEE Transactions on Computers

Volume 33, Issue 9

774 -- 785Bernard Chazelle. Computational Geometry on a Systolic Chip
786 -- 803Lanfranco Lopriore. Capability Based Tagged Architectures
804 -- 811Peter Scheuermann, Geoffrey Wu. Heuristic Algorithms for Broadcasting in Point-to-Point Computer Networks
812 -- 817Stephen S. Yau, Wonmo Hong. Performance Optimization of a CSMA Protocol for Local Computer Networks
818 -- 827Ernst L. Leiss. Data Integrity in Digital Optical Disks
828 -- 834John G. Cleary. Compact Hash Tables Using Bidirectional Linear Probing
835 -- 844André M. Van Tilborg, Larry D. Wittie. Wave Scheduling - Decentralized Scheduling of Task Forces in Multicomputers
845 -- 850Donald T. Tang, Chin-Long Chen. Logic Test Pattern Generation Using Linear Codes
851 -- 855Kei Hiraki, Kenji Nishida, Toshio Shimada. Evaluation of Associative Memory Using Parallel Chained Hashing
855 -- 857Gopal Lakhani. An Improved Distribution Algorithm for Shortest Paths Problem
857 -- 860Charles Delorme, G. Farhi. Large Graphs with Given Degree and Diameter - Part I

Volume 33, Issue 8

685 -- 690Oliver Aberth. Precise Scientific Computation with a Microprocessor
691 -- 699Wesley W. Chu, Min-Tsung Lan, Joseph Hellerstein. Estimation of Intermodule Communication (IMC) and Its Applications in Distributed Processing Systems
700 -- 711Benjamin W. Wah. A Comparative Study of Distributed Resource Sharing on Multiprocessors
712 -- 730Butler W. Lampson. Gene McDaniel, Severo M. Ornstein: An Instruction Fetch Unit for a High-Performance Personal Conmputer
731 -- 736Richard P. Brent, H. T. Kung. Systolic VLSI Arrays for Polynomial GCD Computation
737 -- 741Shigeo Kaneda. A Class of Odd-Weight-Column SEC-DED-S::::b::::ED Codes for Memory System Applications
741 -- 743James E. Smith. On Separable Unordered Codes
743 -- 745Javad Khakbaz. A Testable PLA Design with Low Overhead and High Fault Coverage
745 -- 750Hideo Fujiwara. A New PLA Design for Universal Testability
750 -- 753Balakrishnan Krishnamurthy, Sheldon B. Akers. On the Complexity of Estimating the Size of a Test Set
753 -- 756Javad Khakbaz, Edward J. McCluskey. Self-Testing Embedded Parity Checkers
756 -- 758Gerard G. L. Meyer. A Diagnosis Algorithm for the BGM System Level Fault Model
758 -- 761Teruhiko Yamada, Takashi Nanya. Stuck-At Fault Tests in the Presence of Undetectable Bridging Faults
762 -- 764Syed Zahoor Hassan. Signature Testing of Sequential Machines
765 -- 769D. Michael Miller, Jon C. Muzio. Spectral Fault Signatures for Single Stuck-At Faults in Combinational Networks
769 -- 772A. Yavuz Oruç. A Classification of Cube-Connected Networks with a Simple Control Scheme

Volume 33, Issue 7

592 -- 603Jack B. Dennis, Guang R. Gao, Kenneth W. Todd. Modeling the Weather with a Data Flow Supercomputer
604 -- 612Harold S. Stone. Database Applications ot the FETCH-AND-ADD Instruction
613 -- 618Wael Adi. Fast Burst Error-Correction Scheme with Fire Code
619 -- 625Robert R. Seban, Howard Jay Siegel. Shuffling with the Illiac and PM21 SIMD Networks
626 -- 636Reinhard Männer. Hardware Task/Processor Scheduling in a Polyprocessor Environment
637 -- 645Sartaj Sahni. Scheduling Multipipeline and Multiprocessor Computers
646 -- 651Gianfranco Bilardi, Franco P. Preparata. An Architecture for Bitonic Sorting with Optimal VLSI Performance
652 -- 667Per-Erik Danielsson. Serial/Parallel Convolvers
668 -- 671Joseph JáJá, Robert Michael Owens. VLSI Sorting with Reduced Hardware
671 -- 675Ralf Hartmut Güting, Derick Wood. Finding Rectangle Intersections by Divide-and Conquer
675 -- 677Farhad Hemmati, Donald L. Schilling, George Eichmann. Adjacencies Between the Cycles of a Shift Register with Characteristic Polynomial (1 + ::::x::::):::::::n:::::::
677 -- 679R. R. Shively, W. V. Robinson Jr., D. E. Orton. Cascading Transmission Gates to Enhance Multiplier Performance
679 -- 681Zhiwei Xu. Multivalued Logic and Fuzzy Logic - Their Relationship, Minimization, and Application to Fault Diagnosis
681 -- 0Arne A. Nilsson. Comments on The Reliability of Periodically Repaired ::::n:::: - 1/::::n:::: Parallel Redundant Systems

Volume 33, Issue 6

467 -- 474Jacob Savir, Paul H. Bardell. On Random Pattern Test Length
475 -- 485Dhananjay Brahme, Jacob A. Abraham. Functional Testing of Microprocessors
486 -- 492Anton T. Dahbura, Gerald M. Masson. An ::::O(n:::2.5:::):::: Fault Identification Algorithm for Diagnosable Systems
493 -- 506Yuval Tamir, Carlo H. Séquin. Design and Application of Self-Testing Comparators Implemented with MOS PLA s
518 -- 528Kuang-Hua Huang, Jacob A. Abraham. Algorithm-Based Fault Tolerance for Matrix Operations
529 -- 540Kang G. Shin, Yann-Hang Lee. Error Detection Process - Model, Design, and Its Impact on Computer Performance
541 -- 546Edward J. McCluskey. Verification Testing - A Pseudoexhaustive Test Technique
546 -- 550Joseph L. A. Hughes, Edward J. McCluskey, David J. Lu. Design of Totally Self-Checking Comparators with an Arbitrary Number of Inputs
550 -- 554David G. Furchtgott, John F. Meyer. A Performability Solution Method for Degradable Nonrepairable Systems
554 -- 560John Paul Shen, F. Joel Ferguson. The Design of Easily Tastabel VLSI Array Multipliers
560 -- 564El Mostapha Aboulhamid, Eduard Cerny. Built-In Testing of One-Dimensional Unilateral Iterative Arrays
564 -- 568Paola Velardi, Ravishankar K. Iyer. A Study of Software Failures and Recovery in the MVS Operating System
568 -- 572Cauligi S. Raghavendra, Algirdas Avizienis, Milos D. Ercegovac. Fault Tolerance in Binary Tree Architectures
572 -- 575Hao Dong. Modified Berger Codes for Detection of Unidirectional Errors
575 -- 578Bella Bose, T. R. N. Rao. Unidirectional Error Codes for Shift-Register Memories
578 -- 583Eiji Fujiwara, Nobuo Mutoh, Kohji Matsuoka. A Self-Testing Group-Parity Prediction Checker and Its Use for Built-In Testing
583 -- 588Bella Bose, Der Jei Lin. PLA Implementation of ::::k::::-out-of-::::n:::: Code TSC Checker

Volume 33, Issue 5

377 -- 390Benjamin W. Wah, Y. W. Eva Ma. MANIP - A Multicomputer Architecture for Solving Combinatorial Extremum-Search Problems
391 -- 399Hector Garcia-Molina, Richard J. Lipton, Jacobo Valdes. A Massive Memory Machine
400 -- 403Miguel Angel Fiol, J. Luis A. Yebra, Ignacio Alegre de Miquel. Line Digraph Iterations and the (::::d, k::::) Digraph Problem
404 -- 408Ehud D. Karnin. A Parallel Algorithm for the Knapsack Problem
409 -- 413Robert A. Whiteside, Neil S. Ostlund, Peter G. Hibbard. A Parallel Jacobi Diagonalization Algorithm for a Loop Multiple Processor System
414 -- 426Erling Wold, Alvin M. Despain. Pipeline and Parallel-Pipeline FFT Processors for VLSI Implementations
427 -- 437Franco P. Preparata, Witold Lipski Jr.. Optimal Three-Layer Channel Routing
438 -- 446Balakrishnan Krishnamurthy. An Improved Min-Cut Algorithm for Partitioning VLSI Networks
447 -- 450Karl W. Doty. New Designs for Dense Processor Interconnection Networks
450 -- 455F. S. Wong, Mabo Robert Ito. A Loop-Structured Switching Network
455 -- 462Kouichi Wada, Kenichi Hagihara, Nobuki Tokura. Area-Time Optimal Fast Implementation of Several Functions in a VLSI Model
462 -- 464Alan H. Karp. Exponential and Logarithm by Sequential Squaring

Volume 33, Issue 4

289 -- 300André Thayse. A Matrix Formalism for Asynchronous Implementation of Algorithms
301 -- 313Fred U. Rosenberger, Donald F. Wann. A Computer Aided Procedure for Performing Static Loading Validation of Digital Logic Systems
314 -- 322Robert Michael Tanner. Fault-Tolerant 256K Memory Designs
323 -- 333Laxmi N. Bhuyan, Dharma P. Agrawal. Generalized Hypercube and Hyperbus Structures for a Computer Network
334 -- 343Vijay K. Vaishnavi. Multidimensional Height-Balanced Trees
344 -- 350Norman H. Christ, Anthony E. Terrano. A Very Fast Parallel Processor
351 -- 356Ashok K. Agrawala, Edward G. Coffman Jr., M. R. Garey, Satish K. Tripathi. A Stochastic Optimization Algorithm Minimizing Expected Flow Times on Uniform Processors
357 -- 360C.-S. Yeh, Irving S. Reed, Trieu-Kien Truong. Systolic Multipliers for Finite Fields ::::GF::::(2:::::::m:::::::)
361 -- 364Alberto Apostolico, Alberto Negro. Systolic Algorithms for String Manipulations
364 -- 367Kunio Fukunaga, Shoichiro Yamada, Harold S. Stone, Tamotsu Kasai. A Representation of Hypergraphs in the Euclidean Space
367 -- 373Douglas Stott Parker Jr., C. S. Raghavendra. The Gamma Network
373 -- 374Tom Rhyne. Limitations on Carry Lookahead Networks
374 -- 0Raul Mendez. Benchmarks on Japanese and American Supercomputers - Preliminary Results

Volume 33, Issue 3

201 -- 208Janice E. Cuny, Lawrence Snyder. Testing the Coordination Predicate
209 -- 222Kyu-Young Whang, Gio Wiederhold, Daniel Sagalowicz. Separability - An Approach to Physical Database Design
223 -- 233Seyed H. Hosseini, Jon G. Kuhl, Sudhakar M. Reddy. A Diagnosis Algorithm for Distributed Computing Systems with Dynamic Failure and Repair
234 -- 240S. Louis Hakimi, Kazuo Nakajima. On Adaptive System Diagnosis
241 -- 248John Paul Shen, John P. Hayes. Fault-Tolerance of Dynamic-Full-Access Interconnection Networks
249 -- 260William R. Franta, John R. Heath. Measurement and Analysis of HYPERchannel Networks
261 -- 268Benjamin W. Wah, Kuo-Liang Chen. A Partitioning Approach to the Design of Selection Networks
269 -- 277Guang-Xing Wang, G. Robert Redinbo. Probability of State Transition Errors in a Finite State Machine Containing Soft Failures
278 -- 280F. Warren Burton, Matthew M. Huntbach. Virtual Tree Machines
281 -- 285Pauline Markenscoff. A Deterministic Model for Evaluating the Performance of a Multiple Processor with a Shared Bus
285 -- 0Petr Golan. Design of Totally Self-Checking Checker for 1-out-of-3 Code
286 -- 288Dana Richards. Complexity of Single-Layer Routing

Volume 33, Issue 2

113 -- 124Yann-Hang Lee, Kang G. Shin. Design and Evaluation of a Fault-Tolerant Multiprocessur Using Hardware Recovery Blocks
125 -- 132Makoto Kobayashi. Dynamic Characteristics of Loops
133 -- 139Shahid H. Bokhari. Finding Maximum on an Array Processor with a Global Bus
140 -- 149Steven W. White, Noel R. Strader II, Tom Rhyne. A VLSI-Based I/O Formatting Device
150 -- 159Carol A. Niznik. Performance Evaluation of the Computer Network Dynamic Congestion Table Algorithm
160 -- 177Randal E. Bryant. A Switch-Level Model and Simulator for MOS Digital Systems
190 -- 194Mark Jerrum, Sven Skyum. Families of Fixed Degree Graphs for Processor Interconnection
194 -- 197Pramod K. Varshney, Carlos R. P. Hartmann. Sequential Fault Diagnosis of Modular Systems
197 -- 200Ravishankar K. Iyer. Reliability Evaluation of Fault-Tolerant Systems - Effect of Variability in Failure Rates

Volume 33, Issue 12

1050 -- 1072Steven R. Vegdahl. A Survey of Proposed Architectures for the Execution of Functional Languages
1072 -- 1101D. T. Lee, Franco P. Preparata. Computational Geometry - A Survey
1102 -- 1115John A. Stankovic. A Perspective on Distributed Computer Systems
1116 -- 1129David A. Rennels. Fault-Tolerant Computing - Concepts and Examples
1130 -- 1159Michael Fine, Fouad A. Tobagi. Demand Assignment Multiple Access Schemes in Broadcast Bus Local Area Networks
1160 -- 1179Stanley L. Hurst. Multiple-Valued Logic - Its Status and Its Future
1180 -- 1194Dennis Gannon, John Van Rosendale. On the Impact of Communication Complexity on the Design of Parallel Numerical Algorithms
1195 -- 1220Philip Heidelberger, Stephen S. Lavenberg. Computer Performance Evaluation Methodology
1221 -- 1246John L. Hennessy. VLSI Processor Architecture
1247 -- 1265Charles L. Seitz. Concurrent VLSI Architectures

Volume 33, Issue 11

952 -- 958I. V. Ramakrishnan, Peter J. Varman. Modular Matrix Multiplication on a Linear Array
959 -- 967Arbee L. P. Chen, Victor O. K. Li. Improvement Algorithms for Semijoin Query Processing Programs in Distributed Database Systems
968 -- 976Alexandru Nicolau, Joseph A. Fisher. Measuring the Parallelism Available for Very Long Instruction Word Architectures
977 -- 990Svetlana P. Kartashev, Steven I. Kartashev. Efficient Internode Commucations in Reconfigurable Binary Trees
991 -- 1003Chi-Yuan Chin, Kai Hwang. Packet Switching Networks for Multiprocessors and Data Flow Computers
1004 -- 1012Keki B. Irani, Ibrahim H. Önyüksel. A Closed-Form Solution for the Performance Analysis of Multiple-Bus Multiprocessor Systems
1013 -- 1022Shlomo Weiss, James E. Smith. Instruction Issue Logic in Pipelined Supercomputers
1023 -- 1029Hironori Kasahara, Seinosuke Narita. Practical Multiprocessor Scheduling Algorithms for Efficient Parallel Processing
1030 -- 1033Utpal Banerjee, Daniel Gajski. Fast Execution of Loops with IF Statements
1033 -- 1038Trevor N. Mudge, Humoud B. Al-Sadoun. Memory Interference Models with Variable Connection Time
1038 -- 1041Michael J. Carey, Clark D. Thompson. An Efficient Implementation of Search Trees on (::::lg N:::: + 1) Processors
1041 -- 1045Stephen L. Stepoway, David L. Wells, Gerald R. Kane. A Multiprocessor Architecture for Generating Fractal Surfaces
1045 -- 1048Daniel A. Reed. The Performance of Multimicrocomputer Networks Supporting Dynamic Workloads

Volume 33, Issue 10

861 -- 868André Thayse. Synthesis and Asynchronous Implementation of Algorithms Using a Generalized ::::P::::-Function Concept
869 -- 878Hubert D. Kirrmann, Felix Kaufmann. Poolpo - A Pool of Processors for Process Control Applications
879 -- 894Tsutomu Sasao. Input Variable Assignment and Output Phase Optimization of PLA s
895 -- 905David Lee Tuomenoksa, Howard Jay Siegel. Task Preloading Schemes for Reconfigurable Parallel Processing Systems
906 -- 911In-Shek Hsu, Irving S. Reed, Trieu-Kien Truong, Ke Wang, Chiunn-Shyong Ye, Leslie J. Deutsch. The VLSI Implementation of a Reed-Solomon Encoder Using Berlekamp s Bit-Serial Multiplier Algorithm
912 -- 919Joep L. W. Kessels. Two Designs of a Fault-Tolerant Clocking System
919 -- 922Peter J. Varman, I. V. Ramakrishnan, Donald S. Fussell. A Robust Matrix-Multiplication Array
923 -- 927Balakrishna R. Iyer, J. Bartlett Sinclair. Dynamic Memory Interconnections for Rapid Access
927 -- 931C. C. Guest, M. M. Mirsalehi, Thomas K. Gaylord. Residue Number System Truth-Table Look-Up Processing - Moduli Selection and Logical Minimization
931 -- 934Maurizio A. Bonuccelli, Elena Lodi, Linda Pagli. External Sorting in VLSI
934 -- 937Ten-Chuan Hsiao, Sharad C. Seth. An Analysis of the Use of Rademacher-Walsh Spectrum in Compact Testing
938 -- 939Robert A. Mueller, Vicki H. Allan, Joseph Varghese. The Complexity of Horizontal Word Encoding in Microprogrammed Machines
939 -- 942A. Yavuz Oruç, Deepak Prakash. Routing Algorithms for Cellular Interconnection Arrays
943 -- 947John A. McPherson, Charles R. Kime. Diagnosis in the Presence of Known Faults
947 -- 0Kuang-Wei Chiang, Zvonko G. Vranesic. Comments on Fault Diagnosis of MOS Combinational Networks

Volume 33, Issue 1

2 -- 6D. T. Lee, Joseph Y.-T. Leung. On the 2-Dimensional Channel Assignment Problem
7 -- 20Henk J. Sips. Bit-Sequential Arithmetic for Parallel Processors
21 -- 27Israel Koren, Melvin A. Breuer. On Area and Yield Considerations for Fault-Tolerant VLSI Processor Arrays
28 -- 44Svetlana P. Kartashev, Steven I. Kartashev. Memory Allocations for Multiprocessor Systems That Incorporate Content-Addressable Memories
79 -- 90Jacob Savir, Gary S. Ditlow, Paul H. Bardell. Random Pattern Testability
91 -- 97Giuseppe Caruso. A Local Selection Algorithm for Switching Function Minimization
97 -- 99Corina Reischer, Dan A. Simovici. Graph Functions of Boolean Functions
99 -- 104Carla D. Savage. A Systolic Design for Connectivity Problems
104 -- 107Dan Gordon, Israel Koren, Gabriel M. Silberman. Embedding Tree Stuctures in VLlSI Hexagonal Arrays
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