Journal: IEEE Transactions on Computers

Volume 49, Issue 9

865 -- 885Ganesh Lakshminarayana, Anand Raghunathan, Niraj K. Jha. Behavioral Synthesis of Fault Secure Controller/Datapaths Based on Aliasing Probability Analysis
886 -- 894Cristian Constantinescu. Teraflops Supercomputer: Architecture and Validation of the Fault Tolerance Mechanisms
895 -- 905Hideo Fujiwara. A New Class of Sequential Circuits with Combinational Test Generation Complexity
906 -- 914Frank Liberato, Rami G. Melhem, Daniel Mossé. Tolerance to Multiple Transient Faults for Aperiodic Tasks in Hard Real-Time Systems
915 -- 933Xing Du, Xiaodong Zhang, Zhichun Zhu. Memory Hierarchy Considerations for Cost-Effective Cluster Computing
934 -- 946Chia-Lin Yang, Barton Sano, Alvin R. Lebeck. Exploiting Parallelism in Geometry Processing with General Purpose Processors and Floating-Point SIMD Instructions
947 -- 957Ching-Chih Han, Kang G. Shin, Sang Kyun Yun. On Load Balancing in Multicomputer/Distributed Systems Equipped with Circuit or Cut-Through Switching Capability
958 -- 963Meng-Lai Yin, Douglas M. Blough, Lubomir Bic. A Dependability Analysis for Systems with Global Spares
964 -- 966Sulaiman Al-Bassam. Another Method for Constructing t-EC/AUED Codes
967 -- 970Sung-Ming Yen, Marc Joye. Checking Before Output May Not Be Enough Against Fault-Based Cryptanalysis
971 -- 977Pao-Yuan Chang, Deng-Jyi Chen, Krishna M. Kavi. Multimedia File Allocation on VC Networks Using Multipath Routing
977 -- 979Chiuyuan Chen, Frank K. Hwang. The Minimum Distance Diagram of Double-Loop Networks
980 -- 986Hsien-Sheng Hsiao, Yeh-Hao Chin, Wei-Pang Yang. Reaching Fault Diagnosis Agreement under a Hybrid Fault Model
987 -- 991Saravut Charcranoon, Thomas G. Robertazzi, Serge Luryi. Parallel Processor Configuration Design with Processing/Transmission Costs
992 -- 997Debesh K. Das, Uttam K. Bhattacharya, Bhargab B. Bhattacharya. Isomorph-Redundancy in Sequential Circuits
998 -- 1004Chenggong Charles Fan, Jehoshua Bruck. Tolerating Multiple Faults in Multistage Interconnection Networks with Minimal Extra Stages
1005 -- 0Li Sheng, Jie Wu. A Note on A Tight Lower Bound on the Number of Channels Required for Deadlock-Free Wormhole Routing

Volume 49, Issue 8

769 -- 778Saied Hosseini-Khayat. On Optimal Replacement of Nonuniform Cache Objects
779 -- 797Ravi R. Iyer, Laxmi N. Bhuyan. Design and Evaluation of a Switch Cache Architecture for CC-NUMA Multiprocessors
798 -- 813Guang R. Gao, Vivek Sarkar. Location Consistency-A New Memory Model and Cache Consistency Protocol
814 -- 825Thomas M. Conte, Sumedh W. Sathaye. Properties of Rescheduling Size Invariance for Dynamic Rescheduling-Based VLIW Cross-Generation Compatibility
826 -- 840Paola Bertolazzi, Giuseppe Di Battista, Walter Didimo. Computing Orthogonal Drawings with the Minimum Number of Bends
841 -- 858Brian Field, Taieb Znati, Daniel Mossé. VV-NET: A Versatile Network Architecture for Flexible Delay Guarantees in Real-Time Networks
859 -- 863Christiane Frougny. On-the-Fly Algorithms and Sequential Machines

Volume 49, Issue 7

625 -- 627Israel Koren, Peter Kornerup. Guest Editors Introduction - Special Issue on Computer Arithmetic
628 -- 637Milos D. Ercegovac, Tomás Lang, Jean-Michel Muller, Arnaud Tisserand. Reciprocation, Square Root, Inverse Square Root, and Some Elementary Functions Using Small Multipliers
638 -- 650Guy Even, Peter-Michael Seidel. A Comparison of Three Rounding Algorithms for IEEE Floating-Point Multiplication
651 -- 658Michael Parks. Number-Theoretic Test Generation for Directed Rounding
659 -- 672Fu-Chiung Cheng, Stephen H. Unger, Michael Theobald. Self-Timed Carry-Lookahead Adders
673 -- 680Lampros Kalampoukas, Dimitris Nikolos, Costas Efstathiou, Haridimos T. Vergos, John Kalamatianos. High-Speed Parallel-Prefix Modulo 2n-1 Adders
681 -- 691Michael J. Schulte, Pablo I. Balzola, Ahmet Akkas, Robert W. Brocato. Integer Multiplication with Overflow Detection or Saturation
692 -- 701Wen-Chang Yeh, Chein-Wei Jen. High-Speed Booth Encoded Parallel Multiplier Design
702 -- 715John N. Coleman, E. I. Chester, Christopher I. Softley, Jiri Kadlec. Arithmetic on the European Logarithmic Microprocessor
716 -- 726Chichyang Chen, Rui-Lin Chen, Chih-Huan Yang. Pipelined Computation of Very Large Word-Length LNS Addition/Subtraction with Polynomial Hardware Cost
727 -- 739Elisardo Antelo, Tomás Lang, Javier D. Bruguera. Very-High Radix Circular CORDIC: Vectoring and Unified Rotation/Vectoring
740 -- 748Marc Joye, Sung-Ming Yen. Optimal Left-to-Right Binary Signed-Digit Recoding
749 -- 758M. Anwarul Hasan. Look-Up Table-Based Large Finite Field Multiplication in Memory Constrained Cryptosystems
759 -- 763Milos D. Ercegovac, Laurent Imbert, David W. Matula, Jean-Michel Muller, Guoheng Wei. Improving Goldschmidt Division, Square Root, and Square Root Reciprocal
763 -- 766Erkay Savas, Çetin Kaya Koç. The Montgomery Modular Inverse-Revisited

Volume 49, Issue 6

529 -- 531Fabrizio Lombardi, Mariagiovanna Sami. Guest Editors Introduction
532 -- 541Israel Koren, Zahava Koren. Incorporating Yield Enhancement into the Floorplanning Process
542 -- 552Tadayoshi Horita, Itsuo Takanami. Fault-Tolerant Processor Arrays Based on the 1½-Track Switches with Flexible Spare Distributions
553 -- 559Chor Ping Low. An Efficient Reconfiguration Algorithm for Degradable VLSI/WSI Arrays
560 -- 574Cecilia Metra, Michele Favalli, Bruno Riccò. Self-Checking Detection and Diagnosis of Transient, Delay, and Crosstalk Faults Affecting Bus Lines
575 -- 587Claude Thibeault. On the Adaptation of Viterbi Algorithm for Diagnosis of Multiple Bridging Faults
588 -- 595W. Lynn Gallagher, Earl E. Swartzlander Jr.. Fault-Tolerant Newton-Raphson and Goldschmidt Dividers Using Time Shared TMR
596 -- 607Irith Pomeranz, Sudhakar M. Reddy. Procedures for Static Compaction of Test Sequences for Synchronous Sequential Circuits
608 -- 620B. John Oommen, T. Dale Roberts. Continuous Learning Automata Solutions to the Capacity Assignment Problem

Volume 49, Issue 5

385 -- 386Jean-Luc Gaudiot. Editor s Note
387 -- 397Michael J. Schulte, Earl E. Swartzlander Jr.. A Family of Variable-Precision Interval Arithmetic Processors
398 -- 413Guy Even, Wolfgang J. Paul. On the Design of IEEE Compliant Floating Point Units
414 -- 430Christine Morin, Anne-Marie Kermarrec, Michel Banâtre, Alain Gefflaut. An Efficient and Scalable Approach for Implementing Fault-Tolerant DSM Architectures
431 -- 442Nobuo Tsuda. Fault-Tolerant Processor Arrays Using Additional Bypass Linking Allocated by Graph-Node Coloring
443 -- 464Shi-Yu Huang, Kwang-Ting Cheng, Kuang-Chien Chen, Chung-Yang Huang, Forrest Brewer. AQUILA: An Equivalence Checking System for Large Sequential Designs
465 -- 481Hartej Singh, Ming-Hau Lee, Guangming Lu, Fadi J. Kurdahi, Nader Bagherzadeh, Eliseu M. Chaves Filho. ::::MorphoSys::::: An Integrated Reconfigurable System for Data-Parallel and Computation-Intensive Applications
482 -- 502Anindya Datta, Sang Hyuk Son, Vijay Kumar. Is a Bird in the Hand Worth More than Two in the Bush? Limitations of Priority Cognizance in Conflict Resolution for Firm Real-Time Database Systems
503 -- 518Alper Halbutogullari, Çetin Kaya Koç. Mastrovito Multiplier for General Irreducible Polynomials
519 -- 525Francisco M. Assis, C. E. Pedreira. An Architecture for Computing Zech s Logarithms in GF(2:::m:::)

Volume 49, Issue 4

289 -- 302Franco Fummi, Donatella Sciuto. A Hierarchical Test Generation Approach for Large Controllers
303 -- 316Marco Di Natale, John A. Stankovic. Scheduling Distributed Real-Time Tasks with Minimum Jitter
317 -- 330T. Ramalingom, Krishnaiyan Thulasiraman, Anindya Das. A Matroid-Theoretic Solution to an Assignment Problem in the Conformance Testing of Communication Protocols
331 -- 347Jian Huang, David J. Lilja. Extending Value Reuse to Basic Blocks with Compiler Support
348 -- 359Michael Shyu, Guang-Ming Wu, Yu-Dong Chang, Yao-Wen Chang. Generic Universal Switch Blocks
360 -- 368Laura Heinrich-Litan, Paul Molitor. Least Upper Bounds for the Size of OBDDs Using Symmetry Properties
369 -- 384Todd C. Mowry, Chi-Keung Luk. Understanding Why Correlation Profiling Improves the Predictability of Data Cache Misses in Nonnumeric Applications

Volume 49, Issue 3

193 -- 207Sorin Cotofana, Stamatis Vassiliadis. Signed Digit Addition and Related Operations with Threshold Logic
208 -- 218Zhen Luo, Margaret Martonosi. Accelerating Pipelined Integer and Floating-Point Accumulations in Configurable Hardware with Delayed Addition Techniques
219 -- 229Noboru Takagi, Kyoichi Nakashima. Discrete Interval Truth Values Logic and Its Application
230 -- 245Andrea Bondavalli, Silvano Chiaradonna, Felicita Di Giandomenico, Fabrizio Grandoni 0002. Threshold-Based Mechanisms to Discriminate Transient from Intermittent Faults
246 -- 258San-Yuan Wang, Yu-Chee Tseng. Algebraic Foundations and Broadcasting Algorithms for Wormhole-Routed All-Port Tori
259 -- 266M. Cemil Azizoglu, Ömer Egecioglu. Lower Bounds on Communication Loads with Optimal Placements in Torus Networks
267 -- 276Ugur Kalay, Douglas V. Hall, Marek A. Perkowski. A Minimal Universal Test Set for Self-Test of EXOR-Sum-of-Products Circuits
277 -- 282Ramesh C. Tekumalla, Premachandran R. Menon. On Redundant Path Delay Faults in Synchronous Sequential Circuits
283 -- 284Scott D. Stoller. Leader Election in Asynchronous Distributed Systems

Volume 49, Issue 2

97 -- 99Jean-Luc Gaudiot. Editor s Note
100 -- 111Stefan Poledna, Alan Burns, Andy J. Wellings, Peter Barrett. Replica Determinism and Flexible Scheduling in Hard Real-Time Dependable Systems
112 -- 126Tei-Wei Kuo, Shao-Juen Ho. Similarity-Based Load Adjustment for Static Real-Time Transaction Systems
127 -- 140Lin-Wen Lee, Peter Scheuermann, Radek Vingralek. File Assignment in Parallel I/O Systems with Minimal Variance of Service Time
141 -- 147Vassil S. Dimitrov, Graham A. Jullien, William C. Miller. Complexity and Fast Algorithms for Multiexponentiations
148 -- 159Yi-Bing Lin, Wei-Ru Lai, Rong-Jaye Chen. Performance Analysis for Dual Band PCS Networks
160 -- 169Alpesh Patel, Anthony J. Kusalik, Carl McCrosky. Area-Efficient VLSI Layouts for Binary Hypercubes
170 -- 174Ahmad A. Hiasat. New Efficient Structure for a Modular Multiplier for RNS
175 -- 181Irith Pomeranz, Sudhakar M. Reddy. On the Use of Fully Specified Initial States for Testing of Synchronous Sequential Circuits
182 -- 188Khawar M. Zuberi, Kang G. Shin. Design and Implementation of Efficient Message Scheduling for Controller Area Network

Volume 49, Issue 12

1297 -- 1309Hyesook Lim, Vincenzo Piuri, Earl E. Swartzlander Jr.. A Serial-Parallel Architecture for Two-Dimensional Discrete Cosine and Inverse Discrete Cosine Transforms
1310 -- 1324Stephan Olariu, Maria Cristina Pinotti, Si-Qing Zheng. An Optimal Hardware-Algorithm for Sorting Using a Fixed-Size Parallel Sorting Device
1325 -- 1338Umesh Krishnaswamy, Isaac D. Scherson. A Framework for Computer Performance Evaluation Using Benchmark Sets
1339 -- 1353Tsan-sheng Hsu, Joseph C. Lee, Dian Rae Lopez, William A. Royce. Task Allocation on a Network of Processors
1354 -- 1365William E. Cohen, David W. Hyde, Rhonda Kay Gaede. An Optical Bus-Based Distributed Dynamic Barrier Mechanism
1366 -- 1370Satoshi Fujita. Neighborhood Information Dissemination in the Star Graph
1371 -- 1379Yu-Liang Wu, Hongbing Fan, Malgorzata Marek-Sadowska, C. K. Wong. OBDD Minimization Based on Two-Level Representation of Boolean Functions

Volume 49, Issue 11

1153 -- 1154Ragunathan Rajkumar. Guest Editor s Introduction: 1997 IEEE Real-Time Technologies and Applications Symposium
1155 -- 1169Dong-In Kang, Richard Gerber, Manas Saksena. Parametric Design Synthesis of Distributed Embedded Systems
1170 -- 1183Tarek F. Abdelzaher, Ella M. Atkins, Kang G. Shin. QoS Negotiation in Real-Time Systems and Its Application to Automated Flight Control
1184 -- 1201Monica Brockmeyer, Farnam Jahanian, Constance L. Heitmeyer, Elly Winner. A Flexible, Extensible Simulation Environment for Testing Real-Time Specifications
1202 -- 1214Chia Shen, Ichiro Mizunuma. RT-CRM: Real-Time Channel-Based Reflective Memory
1215 -- 1227Sung-Whan Moon, Jennifer Rexford, Kang G. Shin. Scalable Hardware Priority Queue Architectures for High-Speed Packet Switches
1228 -- 1240Rajagopalan Srinivasan, Sandeep K. Gupta, Melvin A. Breuer. Novel Test Pattern Generators for Pseudoexhaustive Testing
1241 -- 1254Tei-Wei Kuo, Aloysius K. Mok. Real-Time Data Semantics and Similarity-Based Concurrency Control
1255 -- 1271Sally A. McKee, William A. Wulf, James H. Aylor, Robert H. Klenke, Maximo H. Salinas, Sung I. Hong, Dee A. B. Weikle. Dynamic Access Ordering for Streamed Computations
1272 -- 1284Ramesh Karri, Kyosun Kim, Miodrag Potkonjak. Computer Aided Design of Fault-Tolerant Application Specific Programmable Processors
1285 -- 1289Elena Dubrova, Jon C. Muzio. Easily Testable Multiple-Valued Logic Circuits Derived from Reed-Muller Circuits
1290 -- 1292Elena Dubrova, Luca Macchiarulo. A Comment on Graph-Based Algorithm for Boolean Function Manipulation

Volume 49, Issue 10

1009 -- 1012Jean-Luc Gaudiot. Editor s Note
1013 -- 1020Evangelos Kranakis, Andrzej Pelc. Better Adaptive Diagnosis of Hypercubes
1021 -- 1030Keqin Li, Yi Pan. Probabilistic Analysis of Scheduling Precedence Constrained Parallel Tasks on Multicomputers with Contiguous Processor Allocation
1031 -- 1042Mohammad H. Azadmanesh, Roger M. Kieckhafer. Exploiting Omissive Faults in Synchronous Approximate Agreement
1043 -- 1053Bernhard Balkenhol, Stefan Kurtz. Universal Data Compression Based on the Burrows-Wheeler Transformation: Theory and Practice
1054 -- 1063Jun Zhao, V. Swamy Irrinki, Mukesh Puri, Fabrizio Lombardi. Testing SRAM-Based Content Addressable Memories
1064 -- 1073M. Anwarul Hasan, Amr G. Wassal. VLSI Algorithms, Architectures, and Implementation of a Versatile GF(2:::m:::) Processor
1074 -- 1082Naofumi Takagi, Seiji Kuwahara. A VLSI Algorithm for Computing the Euclidean Norm of a 3D Vector
1083 -- 1099Mihalis Psarakis, Dimitris Gizopoulos, Antonis M. Paschalis, Yervant Zorian. Sequential Fault Modeling and Test Pattern Generation for CMOS Iterative Logic Arrays
1100 -- 1109Jovan Dj. Golic, Andrew Clark, Ed Dawson. Generalized Inversion Attack on Nonlinear Filter Generators
1110 -- 1119Ching-Chih Han, Chao-Ju Hou, Kar Shun Tsoi, Sean Ho. Dynamic Establishment and Termination of Real-Time Message Streams in Dual-Bus Networks
1120 -- 1125Chin-Liang Wang, Jyh-Huei Guo. New Systolic Arrays for C + AB2, Inversion, and Division in GF(2:::m:::)
1126 -- 1133Akhil Kumar. An Efficient SuperGrid Protocol for High Availability and Load Balancing
1133 -- 1138Sangho Oh, Chang-Han Kim, Jongin Lim, Dong Hyeon Cheon. Efficient Normal Basis Multipliers in Composite Fields
1139 -- 1145Kun-Jin Lin, Cheng-Wen Wu. A Low-Power CAM Design for LZ Data Compression
1146 -- 1151Marco Tomassini, Moshe Sipper, Mathieu Perrenoud. On the Generation of High-Quality Random Numbers by Two-Dimensional Cellular Automata
1152 -- 0John N. Coleman, E. I. Chester, Christopher I. Softley, Jiri Kadlec. Corrections to Arithmetic on the European Logarithmic Microprocessor

Volume 49, Issue 1

1 -- 15Johnson Kin, Munish Gupta, William H. Mangione-Smith. Filtering Memory References to Increase Energy Efficiency
16 -- 32Mitrajit Chatterjee, Savita Banerjee, Dhiraj K. Pradhan. Buffer Assignment Algorithms on Data Driven ASICs
33 -- 47Asger Munk Nielsen, David W. Matula, Chung Nan Lyu, Guy Even. An IEEE Compliant Floating-Point Adder that Conforms with the Pipelined Packet-Forwarding Paradigm
48 -- 54Wei-Kang Huang, Fred J. Meyer, Fabrizio Lombardi. An Approach for Detecting Multiple Faulty FPGA Logic Blocks
55 -- 64Hagbae Kim, Kang G. Shin. Evaluation of Fault Tolerance Latency from Real-Time Application s Perspectives
65 -- 80Sissades Tongsima, Edwin Hsing-Mean Sha, Chantana Chantrapornchai, David R. Surma, Nelson L. Passos. Probabilistic Loop Scheduling for Applications with Uncertain Execution Time
81 -- 87Tarek F. Abdelzaher, Kang G. Shin. Period-Based Load Partitioning and Assignment for Large Real-Time Applications
88 -- 94Irith Pomeranz, Sudhakar M. Reddy. On Finding a Minimal Functional Description of a Finite-State Machine for Test Generation for Adjacent Machines