| 1933 | -- | 0 | Vijaykrishnan Narayanan. Editorial |
| 1940 | -- | 1953 | Mousumi Bhanja, Baidya Nath Ray. Synthesis Procedure of Configurable Building Block-Based Linear and Nonlinear Analog Circuits |
| 1954 | -- | 1967 | Michael Zwerger, Maximilian Neuner, Helmut Graeb. Analog Power-Down Synthesis |
| 1968 | -- | 1977 | Abhishek Chakraborty, Bodhisatwa Mazumdar, Debdeep Mukhopadhyay. A Combined Power and Fault Analysis Attack on Protected Grain Family of Stream Ciphers |
| 1978 | -- | 1988 | Sangyun Oh, Hongsik Lee, Jongeun Lee. Efficient Execution of Stream Graphs on Coarse-Grained Reconfigurable Architectures |
| 1989 | -- | 2002 | Yongxiang Bao, Mingsong Chen, Qi Zhu, Tongquan Wei, Frédéric Mallet, Tingliang Zhou. Quantitative Performance Evaluation of Uncertainty-Aware Hybrid AADL Designs Using Statistical Model Checking |
| 2003 | -- | 2016 | Duo Liu, Yi Lin, Po-Chun Huang, Xiao Zhu, Liang Liang. Durable and Energy Efficient In-Memory Frequent-Pattern Mining |
| 2017 | -- | 2029 | Priyadarshini Panda, Aayush Ankit, Parami Wijesinghe, Kaushik Roy. FALCON: Feature Driven Selective Classification for Energy-Efficient Image Recognition |
| 2030 | -- | 2043 | Cong Hao, Nan Wang, Takeshi Yoshimura. th in High-Level Synthesis |
| 2044 | -- | 2051 | German Agustin Patterson, J. Sune, E. Miranda. Voltage-Driven Hysteresis Model for Resistive Switching: SPICE Modeling and Circuit Applications |
| 2052 | -- | 2065 | Yu-Min Lee, Chia-Tung Ho. InTraSim: Incremental Transient Simulation of Power Grids |
| 2066 | -- | 2079 | Zhi-Wen Lin, Yao-Wen Chang. Cut Redistribution With Directed-Self-Assembly Templates for Advanced 1-D Gridded Layouts |
| 2080 | -- | 2092 | Iris Hui-Ru Jiang, Hua-Yu Chang. Multiple Patterning Layout Decomposition Considering Complex Coloring Rules and Density Balancing |
| 2093 | -- | 2105 | Gang Wu, Chris Chu. Two Approaches for Timing-Driven Placement by Lagrangian Relaxation |
| 2106 | -- | 2119 | Yun Liang 0001, Wai Teng Tang, Ruizhe Zhao, Mian Lu, Huynh Phung Huynh, Rick Siow Mong Goh. Scale-Free Sparse Matrix-Vector Multiplication on Many-Core Architectures |
| 2120 | -- | 2133 | Ali Ahmadi, Haralampos-G. D. Stratigopoulos, Ke Huang, Amit Nahar, Bob Orr, Michael Pas, John M. Carulli, Yiorgos Makris. Yield Forecasting Across Semiconductor Fabrication Plants and Design Generations |
| 2134 | -- | 2138 | Arman Roohi, Ramtin Zand, Deliang Fan, Ronald F. DeMara. Voltage-Based Concatenatable Full Adder Using Spin Hall Effect Switching |
| 2139 | -- | 2143 | Irith Pomeranz. Close-to-Functional Broadside Tests With a Safety Margin |
| 2144 | -- | 2148 | Yanwen Guo, Xiaoping Wang, Zhigang Zeng. A Compact Memristor-CMOS Hybrid Look-Up-Table Design and Potential Application in FPGA |
| 2149 | -- | 2153 | Weize Yu, Selçuk Köse. False Key-Controlled Aggressive Voltage Scaling: A Countermeasure Against LPA Attacks |