| 1061 | -- | 1074 | Fabrizio Riente, Giovanna Turvani, Marco Vacca, Massimo Ruo Roch, Maurizio Zamboni, Mariagrazia Graziano. ToPoliNano: A CAD Tool for Nano Magnetic Logic |
| 1075 | -- | 1088 | Peter Debacker, Kwangsoo Han, Andrew B. Kahng, Hyein Lee, Praveen Raghavan, Lutong Wang. MILP-Based Optimization of 2-D Block Masks for Timing-Aware Dummy Segment Removal in Self-Aligned Multiple Patterning Layouts |
| 1089 | -- | 1102 | Kan Wang, Sheqin Dong, Fengxian Jiao. TSF3D: MSV-Driven Power Optimization for Application-Specific 3D Network-on-Chip |
| 1103 | -- | 1112 | Wai-Kei Mak, Wan-Sin Kuo, Shi-Han Zhang, Seong-I Lei, Chris Chu. Minimum Implant Area-Aware Placement and Threshold Voltage Refinement |
| 1113 | -- | 1125 | Xiaoqing Xu, Yibo Lin, Meng Li, Jiaojiao Ou, Brian Cline, David Z. Pan. Redundant Local-Loop Insertion for Unidirectional Routing |
| 1126 | -- | 1139 | Vinicius S. Livramento, Derong Liu, Salim Chowdhury, Bei Yu, Xiaoqing Xu, David Z. Pan, José Luís Almada Güntzel, Luiz C. V. dos Santos. Incremental Layer Assignment Driven by an External Signoff Timing Engine |
| 1140 | -- | 1152 | Yibo Lin, Bei Yu, Biying Xu, David Z. Pan. Triple Patterning Aware Detailed Placement Toward Zero Cross-Row Middle-of-Line Conflict |
| 1153 | -- | 1166 | Mohamad Najem, Pascal Benoit, Mohamad El Ahmad, Gilles Sassatelli, Lionel Torres. A Design-Time Method for Building Cost-Effective Run-Time Power Monitoring |
| 1167 | -- | 1180 | Jie Guo, Wujie Wen, Jingtong Hu, Danghui Wang, Hai Helen Li, Yiran Chen. FlexLevel NAND Flash Storage System Design to Reduce LDPC Latency |
| 1181 | -- | 1192 | Yaojun Zhang, Bonan Yan, XiaoBin Wang, Yiran Chen. Persistent and Nonpersistent Error Optimization for STT-RAM Cell Design |
| 1193 | -- | 1202 | Eddie Hung, Tim Todman, Wayne Luk. Transparent In-Circuit Assertions for FPGAs |
| 1203 | -- | 1214 | Renhai Chen, Yi Wang 0003, Jingtong Hu, Duo Liu, Zili Shao, Yong Guan. vFlash: Virtualized Flash for Optimizing the I/O Performance in Mobile Devices |
| 1215 | -- | 1225 | Irith Pomeranz. Identifying Biases of a Defect Diagnosis Procedure |
| 1226 | -- | 1230 | Xiaoping Wang, Bowen Xu, Lin Chen. Efficient Memristor Model Implementation for Simulation and Application |
| 1231 | -- | 1235 | Irith Pomeranz. Clock Sequences for Increasing the Fault Coverage of Functional Test Sequences |