Journal: IEEE Trans. on Circuits and Systems

Volume 58-II, Issue 9

545 -- 549Shreyas Sen, Farshid Aryanfar, Carl Werner. A Multiband Transceiver System in 45-nm CMOS for Extended Data Rate through Notchy Wireline Channels
550 -- 554Chi-Sheng Lin, Ting-Hsu Chien, Chin-Long Wey. A 5.5-GHz 1-mW Full-Modulus-Range Programmable Frequency Divider in 90-nm CMOS Process
555 -- 559Yu Song, Zeljko Ignjatovic. A High-Performance PLL With a Low-Power Active Switched-Capacitor Loop Filter
560 -- 564Doo-Chan Lee, Kyu-Young Kim, Young-Jae Min, Jongsun Park, Soo-Won Kim. A Jitter and Power Analysis on DCO
565 -- 569Chunyuan Zhou, Lei Zhang, Li Zhang, Yan Wang, Zhiping Yu, He Qian. Injection-Locking-Based Power and Speed Optimization of CML Dividers
570 -- 574Martina Mincica, Domenico Pepe, Domenico Zito. CMOS UWB Multiplier
575 -- 579Costas Laoudias, Costas Psychalinos. 1.5-V Complex Filters Using Current Mirrors
580 -- 584Victor R. Gonzalez-Diaz, Fabio Pareschi, Gianluca Setti, Franco Maloberti. A Pseudorandom Number Generator Based on Time-Variant Recursion of Accumulators
585 -- 589Brian Fitzgibbon, Sudhakar Pamarti, Michael Peter Kennedy. A Spur-Free MASH DDSM With High-Order Filtered Dither
590 -- 594Changbing Tang, Fangyue Chen, Xiang Li. Perceptron Implementation of Triple-Valued Logic Operations
595 -- 599Wei Ma, Mingyu Wang, Shuxi Liu, Shan Li, Peng Yu. Stabilizing the Average-Current-Mode-Controlled Boost PFC Converter via Washout-Filter-Aided Method
600 -- 604Rui Guo, Linda DeBrunner. Two High-Performance Adaptive Filter Implementation Schemes Using Distributed Arithmetic
605 -- 609Napapatch Piyachaiyakul, Chalie Charoenlarpnopparut. Nonseparable Three-Dimensional IIR Notch Filter Design Using Outer Product Expansion
610 -- 614Cagatay Candan. Digital Wideband Integrators With Matching Phase and Arbitrarily Accurate Magnitude Response

Volume 58-II, Issue 8

457 -- 461Hyun H. Boo, Sungwon Chung, Joel L. Dawson. Digitally Assisted Feedforward Compensation of Cartesian-Feedback Power-Amplifier Systems
462 -- 466Jiangtao Xu, Carlos E. Saavedra, Guican Chen. An Active Inductor-Based VCO With Wide Tuning Range and High DC-to-RF Power Efficiency
467 -- 471Davide Ponton, Gerhard Knoblinger, Andreas Roithmeier, Frederico Cernoia, Marc Tiebout, Michael Fulde, Pierpaolo Palestri. LC-VCO in the 3.3- to 4-GHz Band Implemented in 32-nm Low-Power CMOS Technology
472 -- 476Sudip Shekhar, Daibashish Gangopadhyay, Eum Chan Woo, David J. Allstot. A 2.4-GHz Extended-Range Type-I SigmaDelta Fractional-N Synthesizer With 1.8-MHz Loop Bandwidth and -110-dBc/Hz Phase Noise
477 -- 481Mi-Jo Kim, Lee-Sup Kim. A 100 MHz-to-1 GHz Fast-Lock Synchronous Clock Generator With DCC for Mobile Applications
482 -- 486Hongrui Wang, Lei Zhang, Li Zhang, Yan Wang, Zhiping Yu. Design of 24-GHz High-Gain Receiver Front-End Utilizing ESD-Split Input Matching Network
487 -- 491Chang-Lin Hsieh, Shen-Iuan Liu. A 1-16-Gb/s Wide-Range Clock/Data Recovery Circuit With a Bidirectional Frequency Detector
492 -- 496Kuo-Hsing Cheng, Jen-Chieh Liu, Hong-Yi Huang, Yu-Liang Li, Yong-Jhen Jhu. A 6-GHz Built-in Jitter Measurement Circuit Using Multiphase Sampler
497 -- 501Jingcheng Zhuang. Low-Blind-Period Differential Sampler for High-Speed Serial Link Receivers
502 -- 506Ko-Chi Kuo, Chi-Wei Wu. A Switching Sequence for Linear Gradient Error Compensation in the DAC Design
507 -- 511Paolo Stefano Crovetti. Finite Common-Mode Rejection in Fully Differential Nonlinear Circuits
512 -- 516Pedro Reviriego, Chris J. Bleakley, Juan Antonio Maestro. Structural DMR: A Technique for Implementation of Soft-Error-Tolerant FIR Filters
517 -- 521Chih-Peng Fan, Chia-Hao Fang, Chia-Wei Chang, Shun-Ji Hsu. Fast Multiple Inverse Transforms With Low-Cost Hardware Sharing Design for Multistandard Video Decoding
522 -- 526Youngjoo Lee, Hoyoung Yoo, In-Cheol Park. Low-Complexity Parallel Chien Search Structure Using Two-Dimensional Optimization
527 -- 531Mahmoudreza Babaei, Hamed Ghasemieh, Mahdi Jalili. Cascading Failure Tolerance of Modular Small-World Networks
532 -- 536Said Boussakta, Monir Taha Hamood. Rader-Brenner Algorithm for Computing New Mersenne Number Transform
537 -- 541M. Zulfiquar A. Bhotto, Andreas Antoniou. Robust Quasi-Newton Adaptive Filtering Algorithms

Volume 58-II, Issue 7

393 -- 397Qun Jane Gu, Heng-Yu Jian, Zhiwei Xu, Yi-Cheng Wu, Mau-Chung Frank Chang, Yves Baeyens, Young-Kai Chen. CMOS Prescaler(s) With Maximum 208-GHz Dividing Speed and 37-GHz Time-Interleaved Dual-Injection Locking Range
398 -- 401Viet-Hoang Le, Hoai-Nam Nguyen, In-Young Lee, Seok-Kyun Han, Sang-Gug Lee. A Passive Mixer for a Wideband TV Tuner
402 -- 406Pere Gilabert, Gabriel Montoro, Eduard Bertran. FPGA Implementation of a Real-Time NARMA-Based Digital Adaptive Predistorter
407 -- 411Jia Hao Cheong, Kok Lim Chan, Pradeep Basappa Khannur, Kei-Tee Tiew, Minkyu Je. A 400-nW 19.5-fJ/Conversion-Step 8-ENOB 80-kS/s SAR ADC in 0.18- muhboxm CMOS
412 -- 416Junhua Shen, Peter R. Kinget. Current-Charge-Pump Residue Amplification for Ultra-Low-Power Pipelined ADCs
417 -- 421Taehwan Oh, Nima Maghari, David Gubbins, Un-Ku Moon. Analysis of Residue Integration Sampling With Improved Jitter Immunity
422 -- 426Jun-Yong Song, Oh-Kyong Kwon. Clock- and Data-Recovery Circuit With Independently Controlled Eye-Tracking Loop for High-Speed Graphic DRAMs
427 -- 431Nikola Zaric, Nedjeljko Lekic, Srdjan Stankovic. An Implementation of the L-Estimate Distributions for Analysis of Signals in Heavy-Tailed Noise
432 -- 436Kanwen Wang, Jialin Chen, Wei Cao, Ying Wang, Lingli Wang, Jiarong Tong. A Reconfigurable Multi-Transform VLSI Architecture Supporting Video Codec Design
437 -- 441Chien-Chen Lin, Yao Li, Chen-Yi Lee. A Predefined Bit-Plane Comparison Coding for Mobile Video Applications
442 -- 446Sangho Shin, Kyosun Kim, Sung-Mo Kang. Reconfigurable Stateful nor Gate for Large-Scale Logic-Array Integrations
447 -- 451Mohammad Saleh Tavazoei. On Monotonic and Nonmonotonic Step Responses in Fractional Order Systems
452 -- 456Bin Zhou, Guang-Ren Duan, Zongli Lin. On Semiglobal Stabilization of Discrete-Time Periodic Systems With Bounded Controls

Volume 58-II, Issue 6

321 -- 325Chao-Ching Hung, Shen-Iuan Liu. A 40-GHz Fast-Locked All-Digital Phase-Locked Loop Using a Modified Bang-Bang Algorithm
326 -- 330Liming Xiu, Ming Lin, Hong Jiang. A Storage-Based Carry Randomization Technique for Spurs Reduction in Flying-Adder Frequency Synthesizer
331 -- 335Stefan Tertinek, Orla Feely. Output-Jitter Performance of Second-Order Digital Bang-Bang Phase-Locked Loops With Nonaccumulative Reference Clock Jitter
336 -- 340Tsutomu Tanzawa. A Switch-Resistance-Aware Dickson Charge Pump Model for Optimizing Clock Frequency
341 -- 345Marko Neitola, Timo Rahkonen. Predicting and Avoiding Spurious Tones in a DWA-Mismatch-Shaping DAC
346 -- 350Nan Sun. High-Order Mismatch-Shaping in Multibit DACs
351 -- 355Esther Rodríguez-Villegas, Alexander J. Casson, Phil Corbishley. A Subhertz Nanopower Low-Pass Filter
356 -- 360Indrit Myderrizi, Shahram Minaei, Erkan Yüce. An Electronically Fine-Tunable Multi-Input-Single-Output Universal Filter
361 -- 365Won Young Lee, Lee-Sup Kim. A Spread Spectrum Clock Generator for DisplayPort Main Link
366 -- 370Constantin Paleologu, Jacob Benesty, Silviu Ciochina. Regularization of the Affine Projection Algorithm
371 -- 375Raveendranatha P. Mahesh, A. Prasad Vinod. A Low-Complexity Flexible Spectrum-Sensing Scheme for Mobile Cognitive Radio Terminals
376 -- 380Chen Zheng, Dongsheng Ma. Design of a Monolithic Automatic Substrate/Supply Multiplexer for DVS-Enabled Adaptive Power Converters
381 -- 385Zbigniew Galias, Xinghuo Yu. Study of Periodic Solutions in Discretized Two-Dimensional Sliding-Mode Control Systems
386 -- 390Yanbo Gao, Binghua Sun, Guoping Lu. Passivity-Based Integral Sliding-Mode Control of Uncertain Singularly Perturbed Systems

Volume 58-II, Issue 5

249 -- 253Jae-Jin Lee, Chul Soon Park. 60-GHz Gigabits-Per-Second OOK Modulator With High Output Power in 90-nm CMOS
254 -- 258Eleni-Sotiria Kytonaki, Yannis Papananos. A Low-Voltage Differentially Tuned Current-Adjusted 5.5-GHz Quadrature VCO in 65-nm CMOS Technology
259 -- 263Aliakbar Ghadiri, Kambiz K. Moez. Compact Transformer-Based Distributed Amplifier for UWB Systems
264 -- 268Mincheol Seo, Kyungwon Kim, Min-Su Kim, Hyungchul Kim, Jeongbae Jeon, Myung-Kyu Park, Hyojoon Lim, Youngoo Yang. Ultrabroadband Linear Power Amplifier Using a Frequency-Selective Analog Predistorter
269 -- 273Jong-Hoon Kim, Jung-Bum Shin, Jae-Yoon Sim, Hong June Park. 5-Gb/s Peak Detector Using a Current Comparator and a Three-State Charge Pump
274 -- 278Chang-Seob Shin, Gil-Cho Ahn. A 10-bit 100-MS/s Dual-Channel Pipelined ADC Using Dynamic Memory Effect Cancellation Technique
279 -- 283Sandhya Purighalla, Brent Maundy. 84-dB Range Logarithmic Digital-to-Analog Converter in CMOS 0.18- muhboxm Technology
284 -- 288Shanthi Pavan. On Continuous-Time DeltaSigma Modulators With Return-to-Open DACs
289 -- 293Jingcheng Zhuang, Bruce Andrew Doyle, Emerson S. Fang. Linear Equalization and PVT-Independent DC Wander Compensation for AC-Coupled PCIe 3.0 Receiver Front End
294 -- 298Yu Pu, Xin Zhang, Katsuyuki Ikeuchi, Atsushi Muramatsu, Atsushi Kawasumi, Makoto Takamiya, Masahiro Nomura, Hirofumi Shinohara, Takayasu Sakurai. Post-Silicon Clock Deskew Employing Hot-Carrier Injection Trimming With On-Chip Skew Monitoring and Auto-Stressing Scheme for Sub/Near Threshold Digital Circuits
299 -- 303Hiroshi Fuketa, Dan Kuroda, Masanori Hashimoto, Takao Onoye. An Average-Performance-Oriented Subthreshold Processor Self-Timed by Memory Read Completion
304 -- 308Hou-Jen Ko, Shen-Fu Hsiao. Design and Application of Faithfully Rounded and Truncated Multipliers With Combined Deletion, Reduction, Truncation, and Rounding
309 -- 313Kyun-Sang Park, Jong-Tae Lim. Stability Analysis of Nonstandard Nonlinear Singularly Perturbed Discrete Systems
314 -- 318Simin Yu, Jinhu Lu, Guanrong Chen, Xinghuo Yu. Generating Grid Multiwing Chaotic Attractors by Constructing Heteroclinic Loops Into Switching Systems

Volume 58-II, Issue 4

189 -- 194Peng Wei, Wenyi Che, Zhongyu Bi, Chen Wei, Yan Na, Li Qiang, Min Hao. High-Efficiency Differential RF Front-End for a Gen2 RFID Tag
195 -- 199Mury Thian, Vincent F. Fusco. Transmission-Line Class-E Power Amplifier With Extended Maximum Operating Frequency
200 -- 204Davide Tasca, Marco Zanuso, Salvatore Levantino, Carlo Samori, Andrea L. Lacaita. Low-Power Divider Retiming in a 3-4 GHz Fractional-N PLL
205 -- 209Nagendra Krishnapura, Abhishek Agrawal, Sameer Singh. A High-IIP3 Third-Order Elliptic Filter With Current-Efficient Feedforward-Compensated Opamps
210 -- 214Zuow-Zun Chen, Tai-Cheng Lee. The Study of a Dual-Mode Ring Oscillator
215 -- 219Chung-Yi Li, Yuan-Ho Chen, Tsin-Yuan Chang, Jyun-Neng Chen. A Probabilistic Estimation Bias Circuit for Fixed-Width Booth Multiplier and Its DCT Applications
220 -- 224Hyeong-Ju Kang, Seung Jae Lee, Byung-Do Yang. Area-Efficient Prefilter Architecture for a CDMA Receiver
225 -- 229Evgueni Doukhnitch, Emre Ozen. Hardware-Oriented Algorithm for Quaternion-Valued Matrix Decomposition
230 -- 234Hiroshi Makino, Shunji Nakata, Hirotsugu Suzuki, Shin'ichiro Mutoh, Masayuki Miyama, Tsutomu Yoshimura, Shuhei Iwade, Yoshio Matsuda. Reexamination of SRAM Cell Write Margin Definitions in View of Predicting the Distribution
235 -- 239David Wolpert, Paul Ampadu. A Sensor System to Detect Positive and Negative Current-Temperature Dependences
240 -- 243Julien Clinton Sprott. A New Chaotic Jerk Circuit
244 -- 248Yuan-Ta Hsieh, Bin-Da Liu, Jian-Fu Wu, Chiao-Li Fang, Hann-Huei Tsai, Ying-Zong Juang. A High Current Accuracy Boost White LED Driver Based on Offset Calibration Technique

Volume 58-II, Issue 3

129 -- 133José M. Muñoz-Ferreras, Roberto Gómez-Garcia, Félix Pérez-Martínez. RF Front-End Concept and Implementation for Direct Sampling of Multiband Signals
134 -- 138Jun Wu, Peichen Jiang, Dongpo Chen, Jianjun Zhou. A Dual-Band GNSS RF Front End With a Pseudo-Differential LNA
139 -- 143Chao-Ching Hung, Shen-Iuan Liu. A Noise Filtering Technique for Fractional-N Frequency Synthesizers
144 -- 148Wu-Hsin Chen, Byunghoo Jung. High-Speed Low-Power True Single-Phase Clock Dual-Modulus Prescalers
149 -- 153Ching-Che Chung, Chiun-Yao Ko, Sung-En Shen. Built-in Self-Calibration Circuit for Monotonic Digitally Controlled Oscillator Design in 65-nm CMOS Technology
154 -- 158Federico Bizzarri, Angelo Brambilla, Giancarlo Storti Gajani. Phase Noise Simulation in Analog Mixed Signal Circuits: An Application to Pulse Energy Oscillators
159 -- 163Armin Tajalli, Yusuf Leblebici. Low-Power and Widely Tunable Linearized Biquadratic Low-Pass Transconductor-C Filter
164 -- 168Cristina Azcona, Belén Calvo, Nicolás J. Medrano-Marqués, Alberto Bayo, Santiago Celma. 12-b Enhanced Input Range On-Chip Quasi-Digital Converter With Temperature Compensation
169 -- 173Manho Kim, Hyunjoong Lee, Jong-Kwan Woo, Nan Xing, Min-Oh Kim, Suhwan Kim. A Low-Cost and Low-Power Time-to-Digital Converter Using Triple-Slope Time Stretching
174 -- 178Marco Ho, Ka Nang Leung. Dynamic Bias-Current Boosting Technique for Ultralow-Power Low-Dropout Regulator in Biomedical Applications
179 -- 183G. S. Visweswaran, Pragya Varshney, Maneesha Gupta. New Approach to Realize Fractional Power in z-Domain at Low Frequency
184 -- 188Yimin Zhou, Yu Sun 0003, Zhidan Feng, Shixin Sun. PID-Based Bit Allocation Strategy for H.264/AVC Rate Control

Volume 58-II, Issue 2

65 -- 69Ching-Yuan Yang, Chih-Hsiang Chang, Jun-Hong Weng, Hsin-Ming Wu. A 0.5/0.8-V 9-GHz Frequency Synthesizer With Doubling Generation in 0.13-μm CMOS
70 -- 74Young Hun Seo, Seon-Kyoo Lee, Jae-Yoon Sim. A 1-GHz Digital PLL With a 3-ps Resolution Floating-Point-Number TDC in a 0.18-μm CMOS
75 -- 79Rahul Singh, Yves Audet, Yves Gagnon, Yvon Savaria, Étienne Boulais, Michel Meunier. A Laser-Trimmed Rail-to-Rail Precision CMOS Operational Amplifier
80 -- 84Man Kay Law, Amine Bermak, Chao Shi. A Low-Power Energy-Harvesting Logarithmic CMOS Image Sensor With Reconfigurable Resolution Using Two-Level Quantization Scheme
85 -- 89Arthur Spivak, Alexander Belenky, Alexander Fish, Orly Yadid-Pecht. A Wide-Dynamic-Range CMOS Image Sensor With Gating for Night Vision Systems
90 -- 94Dong-Yong Shin, Hyunjoong Lee, Suhwan Kim. A Delta-Sigma Interface Circuit for Capacitive Sensors With an Automatically Calibrated Zero Point
95 -- 99Chun-Fu Liao, Yuan-Hao Huang. Power-Saving 4 ˟ 4 Lattice-Reduction Processor for MIMO Detection With Redundancy Checking
100 -- 104Aaron E. Cohen, Keshab K. Parhi. Secure Variable Data Rate Transmission
105 -- 109Ching-Che Chung, Cheng-Ruei Yang. An Autocalibrated All-Digital Temperature Sensor for On-Chip Thermal Monitoring
110 -- 114Jianyong Chen, Junwei Zhou, Kwok-Wo Wong. A Modified Chaos-Based Joint Compression and Encryption Scheme
115 -- 119Massimiliano Laddomada, D. E. Troncoso, Gordana Jovanovic-Dolecek. Design of Multiplierless Decimation Filters Using an Extended Search of Cyclotomic Polynomials
120 -- 124Shing-Chow Chan, Z. G. Zhang, Y. J. Chu. A New Transform-Domain Regularized Recursive Least M-Estimate Algorithm for a Robust Linear Estimation

Volume 58-II, Issue 12

785 -- 786Gabriel A. Rincón-Mora. Introduction to the Special Section on Energy-Harvesting/Scavenging Circuits and Systems
787 -- 791Rajiv Damodaran Prabha, Dongwon Kwon, Orlando Lazaro, Karl D. Peterson, Gabriel A. Rincón-Mora. Increasing Electrical Damping in Energy-Harnessing Transducers
792 -- 796Paul D. Mitcheson, Tzern T. Toh, Kwok H. Wong, Steve G. Burrow, Andrew S. Holmes. Tuning the Resonant Frequency and Damping of an Electromagnetic Energy Harvester Using Power Electronics
797 -- 801Antônio Carlos M. de Queiroz, Marcelo Domingues. The Doubler of Electricity Used as Battery Charger
802 -- 806Jungmoon Kim, Jihwan Kim, Chulwoo Kim. A Regulated Charge Pump With a Low-Power Integrated Optimum Power Point Tracking Algorithm for Indoor Solar Energy Harvesting
807 -- 811Mina Danesh, John R. Long. Photovoltaic Antennas for Autonomous Wireless Systems
812 -- 816Hongcheng Xu, Maurits Ortmanns. A Temperature and Process Compensated Ultralow-Voltage Rectifier in Standard Threshold CMOS for Energy-Harvesting Applications
817 -- 821Chin-Lung Yang, Yu-Lin Yang, Chun-Chih Lo. Subnanosecond Pulse Generators for Impulsive Wireless Power Transmission and Reception
822 -- 826Erez Falkenstein, Daniel Costinett, Regan Zane, Zoya Popovic. Far-Field RF-Powered Variable Duty Cycle Wireless Sensor Platform
827 -- 831Chao Shi, Brian Miller, Kartikeya Mayaram, Terri S. Fiez. A Multiple-Input Boost Converter for Low-Power Energy Harvesting
832 -- 836Yi-Chun Shih, Brian P. Otis. An Inductorless DC-DC Converter for Energy Harvesting With a 1.2-µW Bandgap-Referenced Output Controller
837 -- 841Jorge Pernillo, Michael P. Flynn. A 1.5-GS/s Flash ADC With 57.7-dB SFDR and 6.4-Bit ENOB in 90 nm Digital CMOS
842 -- 846Gui Liu, Roc Berenguer, Yang Xu. A MM-Wave Configurable VCO Using MCPW-Based Tunable Inductor in 65-nm CMOS
847 -- 851Xuan Zhang, Ishita Mukhopadhyay, Rajeev K. Dokania, Alyssa B. Apsel. A 46-µW Self-Calibrated Gigahertz VCO for Low-Power Radios
852 -- 856Alireza Kheirkhahi, Payam Naghshtabrizi, Lawrence E. Larson. Stability Analysis of RF Power Amplifier Envelope Feedback
857 -- 861Bobae Kim, Cholho Kwak, Jongsoo Lee. A Dual-Mode Power Amplifier With On-Chip Switch Bias Control Circuits for LTE Handsets
862 -- 866Manel Ben-Romdhane, Chiheb Rebai, Adel Ghazel, Patricia Desgreys, Patrick Loumeau. Nonuniformly Controlled Analog-to-Digital Converter for SDR Multistandard Radio Receiver
867 -- 871Chan-Hsiang Weng, Chen-Chien Lin, Yu-Cheng Chang, Tsung-Hsien Lin. A 0.89-mW 1-MHz 62-dB SNDR Continuous-Time Delta-Sigma Modulator With an Asynchronous Sequential Quantizer and Digital Excess-Loop-Delay Compensation
872 -- 876Nan Sun, Peiyan Cao. Low-Complexity High-Order Vector-Based Mismatch Shaping in Multibit ΔΣ ADCs
877 -- 881Athanasios Stefanou, Georges G. E. Gielen. A Volterra Series Nonlinear Model of the Sampling Distortion in Flash ADCs Due to Substrate Noise Coupling
882 -- 886S. Balasubramanian, Gregory L. Creech, J. Wilson, S. M. Yoder, Jamin J. McCue, Marian Verhelst, Waleed Khalil. Systematic Analysis of Interleaved Digital-to-Analog Converters
887 -- 891Hyunsik Kim, Jinyong Jeon, Sungwoo Lee, Junhyeok Yang, Seung-Tak Ryu, Gyu-Hyeong Cho. A Compact-Sized 9-Bit Switched-Current DAC for AMOLED Mobile Display Drivers
892 -- 896César Sánchez-Perez, Jesus de Mingo, Paloma Garcia Ducar, Pedro Luis Carro, Antonio Valdovinos. Dynamic Load Modulation With a Reconfigurable Matching Network for Efficiency Improvement Under Antenna Mismatch
897 -- 901Chang-Lin Hsieh, Shen-Iuan Liu. Decision Feedback Equalizers Using the Back-Gate Feedback Technique
902 -- 905Hitesh Shrimali, Shouri Chatterjee. Distortion Analysis of a Three-Terminal MOS-Based Discrete-Time Parametric Amplifier
906 -- 910Kiarash Gharibdoust, Mehrdad Sharif Bakhtiar. A Method for Noise Reduction in Active-RC Circuits
911 -- 915Alex S. Weddell, Geoff V. Merrett, Tom J. Kazmierski, Bashir M. Al-Hashimi. Accurate Supercapacitor Modeling for Energy Harvesting Wireless Sensor Nodes
916 -- 920Ruimin Huang, Chip-Hong Chang, Mathias Faust, Niklas Lotze, Yiannos Manoli. Sign-Extension Avoidance and Word-Length Optimization by Positive-Offset Representation for FIR Filter Design
921 -- 925Jun-Yong Song, Oh-Kyong Kwon. Low-Power 10-Gb/s Transmitter for High-Speed Graphic DRAMs Using 0.18-µm CMOS Technology
926 -- 930Goran Molnar, Mladen Vucic. Closed-Form Design of CIC Compensators Based on Maximally Flat Error Criterion
931 -- 935Chang-Chun Hua, Xian Yang, Jing Yan, Xin-Ping Guan. New Exponential Stability Criteria for Neural Networks With Time-Varying Delay
936 -- 940Chengtao Wen, Xiaoyan Ma. A Canonical Piecewise-Linear Representation Theorem: Geometrical Structures Determine Representation Capability

Volume 58-II, Issue 11

709 -- 713Chengwu Tao, Ayman A. Fayed. A Buck Converter With Reduced Output Spurs Using Asynchronous Frequency Hopping
714 -- 718Kaveh Hosseini, Brian Fitzgibbon, Michael Peter Kennedy. Observations Concerning the Generation of Spurious Tones in Digital Delta-Sigma Modulators Followed by a Memoryless Nonlinearity
719 -- 723Xiaojun Bi, Yongxin Guo, James Brinkhoff, Lin Jia, Lei Wang, Yong-Zhong Xiong, Mook-Seng Leong, Fujiang Lin. A 60-GHz 1-V Supply Band-Tunable Power Amplifier in 65-nm CMOS
724 -- 728Ippei Akita, Tetsuro Itakura, Kei Shiraishi. Current-Steering Digital-to-Analog Converter With a High-PSRR Current Switch
729 -- 733Keping Wang, Zhigong Wang, XueMei Lei, Xiang Cao, Peng Han, Geliang Yang, Kaixue Ma, Kiat Seng Yeo. A Low-Loss Image-Reject Mixer Using Source Follower Isolation Method for DRM/DAB Tuner Applications
734 -- 738A. K. Gupta, K. Nagaraj, T. R. Viswanathan. A Two-Stage ADC Architecture With VCO-Based Second Stage
739 -- 743Selçuk Köse, Eby G. Friedman. Effective Resistance of a Two Layer Mesh
744 -- 747Skyler Weaver, Benjamin P. Hershberg, Nima Maghari, Un-Ku Moon. Domino-Logic-Based ADC for Digital Synthesis
748 -- 752Pascal Witte, John G. Kauffman, Joachim Becker, Maurits Ortmanns. A Correlation-Based Background Error Estimation Technique for Bandpass Delta-Sigma ADC DACs
753 -- 757Guoliang Wei, Zidong Wang, Bo Shen, Maozhen Li. Probability-Dependent Gain-Scheduled Filtering for Stochastic Systems With Missing Measurements
758 -- 762Dali Chen, Yangquan Chen, Dingyu Xue. Digital Fractional Order Savitzky-Golay Differentiator
763 -- 767Kwang-Hoon Kim, Young-Seok Choi, Seong-Eun Kim, Woo-Jin Song. An Affine Projection Algorithm With Periodically Evolved Update Interval
768 -- 772Arsenia Chorti, Mike Brookes. On the Effect of Voigt Profile Oscillators on OFDM Systems
773 -- 777Ali Montazeri, Allen Webb, Kamran Kiasaleh. Low-Power Spectral-Line Clock Recovery Algorithm for SDR Applications
778 -- 782Huy-Binh Le, Xuan-Dien Do, Sang-Gug Lee, Seung-Tak Ryu. A Long Reset-Time Power-On Reset Circuit With Brown-Out Detection Capability

Volume 58-II, Issue 10

617 -- 621Bo-Yu Lin, Shen-Iuan Liu. A 132.6-GHz Phase-Locked Loop in 65 nm Digital CMOS
622 -- 626Nawreen Khan, Masum Hossain, K. L. Eddie Law. A Low Power Frequency Synthesizer for 60-GHz Wireless Personal Area Networks
627 -- 631Yushi Zhou, Fei Yuan. A Study of the Lock Range of Injection-Locked CMOS Active-Inductor Oscillators Using a Linear Control System Approach
632 -- 636Seong-Young Seo, Jung-Hoon Chun, Young-Hyun Jun, Seok Kim, Kee-Won Kwon. A Digitally Controlled Oscillator With Wide Frequency Range and Low Supply Sensitivity
637 -- 641Wei-Hao Sung, Jui-Yuan Yu, Chen-Yi Lee. A Robust Frequency Tracking Loop for Energy-Efficient Crystalless WBAN Systems
642 -- 646Jonas Fritzin, Ylva Jung, Per Niklas Landin, Peter Handel, Martin Enqvist, Atila Alvandpour. Phase Predistortion of a Class-D Outphasing RF Amplifier in 90 nm CMOS
647 -- 651Giorgio Leuzzi, Vincenzo Stornelli, Stefano Del Re. A Tuneable Active Inductor With High Dynamic Range for Band-Pass Filter Applications
652 -- 656Martin Clara, Nicola Da Dalt. Jitter Noise of Sampled Multitone Signals
657 -- 661Mario Garrido, Jesús Grajal, Oscar Gustafsson. Optimum Circuits for Bit Reversal
662 -- 666Mario Garrido, Oscar Gustafsson, Jesús Grajal. Accurate Rotations Based on Coefficient Scaling
667 -- 671Davide De Caro, Nicola Petra, Antonio G. M. Strollo. Efficient Logarithmic Converters for Digital Signal Processing Applications
672 -- 676Chung-Hsun Huang, Tzung-Lin Wu, Yi-Ming Wang. Adaptive Pseudo Dual Keeper for Wide Fan-In Dynamic Circuits
677 -- 681Takashi Matsubara, Hiroyuki Torikai, Tetsuya Hishiki. A Generalized Rotate-and-Fire Digital Spiking Neuron Model and Its On-FPGA Learning
682 -- 686Yi-Min Lin, Chi-Heng Yang, Chih-Hsiang Hsu, Hsie-Chia Chang, Chen-Yi Lee. A MPCN-Based Parallel Architecture in BCH Decoders for nand Flash Memory Devices
687 -- 691Hyung-Joon Chi, Young-Ho Choi, Soo-Min Lee, Jae-Yoon Sim, Hong June Park, Jong-Jin Lim, Pil-Sung Kang, Bu-Yeol Lee, Jin-Cheol Hong, Hee-Sub Lee. A 2-Gb/s Intrapanel Interface for TFT-LCD With a VSYNC-Embedded Subpixel Clock and a Cascaded Deskew and Multiphase DLL
692 -- 696Tian-Bo Deng. Minimax Design of Low-Complexity Even-Order Variable Fractional-Delay Filters Using Second-Order Cone Programming
697 -- 701Kian Haghdad, Mohab Anis. Power Supply Pads Assignment for Maximum Timing Yield
702 -- 706Xiaoming Chen, Wei Wu, Yu Wang 0002, Hao Yu, Huazhong Yang. An EScheduler-Based Data Dependence Analysis and Task Scheduling for Parallel Circuit Simulation

Volume 58-II, Issue 1

1 -- 5Wei-Hsin Tseng, Jieh-Tsorng Wu, Yung-Cheng Chu. A CMOS 8-Bit 1.6-GS/s DAC With Digital Random Return-to-Zero
6 -- 10Brian Fitzgibbon, Michael Peter Kennedy. Calculation of Cycle Lengths in Higher Order Error Feedback Modulators With Constant Inputs
11 -- 15Jui-Yi Lin, Hwann-Kaeo Chiou. Power-Constrained Third-Order Active Notch Filter Applied in IR-LNA for UWB Standards
16 -- 20Shinichi Hori, Boris Murmann. Feedforward Interference Cancellation Architecture for Short-Range Wireless Communication
21 -- 25José M. Algueta Miguel, Carlos Aristoteles De la Cruz-Blas, Antonio J. López-Martín. Fully Differential Current-Mode CMOS Triode Translinear Multiplier
26 -- 30Yikai Wang, M. Koen, Dongsheng Ma. Low-Noise CMOS TGC Amplifier With Adaptive Gain Control for Ultrasound Imaging Receivers
31 -- 35Rafal Dlugosz, Tomasz Talaska, Witold Pedrycz. Current-Mode Analog Adaptive Mechanism for Ultra-Low-Power Neural Networks
36 -- 40Qiaoyan Yu, Paul Ampadu. A Dual-Layer Method for Transient and Permanent Error Co-Management in NoC Links
41 -- 45Dakshina Murthy-Bellur, Marian K. Kazimierczuk. Isolated Two-Transistor Zeta Converter With Reduced Transistor Voltage Stress
46 -- 50Håkan Johansson. Farrow-Structure-Based Reconfigurable Bandpass Linear-Phase FIR Filters for Integer Sampling Rate Conversion
51 -- 55Xiaoping Lai, Zhiping Lin, Hon Keung Kwan. A Sequential Minimization Procedure for Minimax Design of IIR Filters Based on Second-Order Factor Updates
56 -- 61Tsung-Hsien Liu, Jin-Yi Jiang, Yuan-Sun Chu. A Low-Cost MMSE-SIC Detector for the MIMO System: Algorithm and Hardware Implementation