| 1 | -- | 32 | Amit Chowdhary, John P. Hayes. General technology mapping for field-programmable gate arrays based on lookup tables |
| 33 | -- | 57 | Maria K. Michael, Spyros Tragoudas. ATPG tools for delay faults at the functional level |
| 58 | -- | 90 | Roman L. Lysecky, Frank Vahid. Prefetching for improved bus wrapper performance in cores |
| 91 | -- | 121 | Shantanu Dutt, Wenyong Deng. Cluster-aware iterative improvement techniques for partitioning large VLSI circuits |
| 122 | -- | 136 | Laurence Goodby, Alex Orailoglu, Paul M. Chau. Microarchitectural synthesis of performance-constrained, low-power VLSI designs |
| 137 | -- | 158 | Luís Guerra e Silva, João P. Marques Silva, Luis Miguel Silveira, Karem A. Sakallah. Satisfiability models and algorithms for circuit delay computation |
| 159 | -- | 172 | Alain Darte, Robert Schreiber, B. Ramakrishna Rau, Frédéric Vivien. Constructing and exploiting linear schedules with prescribed parallelism |
| 173 | -- | 188 | Ashok Jagannathan, Sung-Woo Hur, John Lillis. A fast algorithm for context-aware buffer insertion |
| 189 | -- | 216 | Ranga Vemuri, Srinivas Katkoori, Meenakshi Kaul, Jay Roy. An efficient register optimization algorithm for high-level synthesis from hierarchical behavioral specifications |
| 217 | -- | 230 | Shi-Zheng Eric Lin, Chieh Changfan, Yu-Chin Hsu, Fur-Shing Tsai. Optimal time borrowing analysis and timing budgeting optimization for latch-based designs |