| 1 | -- | 9 | Craig Schlottmann, David N. Abramson, Paul E. Hasler. A MITE-Based Translinear FPAA |
| 10 | -- | 18 | Craig Schlottmann, Csaba Petre, Paul E. Hasler. A High-Level Simulink-Based Tool for FPAA Configuration |
| 19 | -- | 28 | Hongbin Sun, Chuanyin Liu, Wei Xu, Jizhong Zhao, Nanning Zheng, Tong Zhang 0002. Using Magnetic RAM to Build Low-Power and Soft Error-Resilient L1 Cache |
| 29 | -- | 41 | Afshin Nourivand, Asim J. Al-Khalili, Yvon Savaria. Postsilicon Tuning of Standby Supply Voltage in SRAMs to Reduce Yield Losses Due to Parametric Data-Retention Failures |
| 42 | -- | 51 | Maurice Meijer, José Pineda de Gyvez. Body-Bias-Driven Design Strategy for Area- and Performance-Efficient CMOS Circuits |
| 52 | -- | 65 | Kubilay Atasu, Wayne Luk, Oskar Mencer, Can C. Özturan, Günhan Dündar. FISH: Fast Instruction SyntHesis for Custom Processors |
| 66 | -- | 79 | Jinwook Jang, Olivier Franza, Wayne Burleson. Compact Expressions for Supply Noise Induced Period Jitter of Global Binary Clock Trees |
| 80 | -- | 88 | Kun-Hung Tsai, Shen-Iuan Liu. A 104-GHz Phase-Locked Loop Using a VCO at Second Pole Frequency |
| 89 | -- | 97 | Wei Yao, Yiyu Shi, Lei He, Sudhakar Pamarti. Worst-Case Estimation for Data-Dependent Timing Jitter and Amplitude Noise in High-Speed Differential Link |
| 98 | -- | 111 | Zheng Li, Moustafa Mohamed, Xi Chen, Eric Dudley, Ke Meng, Li Shang, Alan Rolf Mickelson, Russ Joseph, Manish Vachharajani, Brian Schwartz, Yihe Sun. Reliability Modeling and Management of Nanophotonic On-Chip Networks |
| 112 | -- | 125 | Hassan Salmani, Mohammad Tehranipoor, Jim Plusquellic. A Novel Technique for Improving Hardware Trojan Detection and Reducing Trojan Activation Time |
| 126 | -- | 134 | Geng-Ming Chiu, James Chien-Mo Li. A Secure Test Wrapper Design Against Internal and Boundary Scan Attacks for Embedded Cores |
| 135 | -- | 147 | Mahdi Shabany, P. Glenn Gulak. A 675 Mbps, 4 $\times$ 4 64-QAM K-Best MIMO Detector in 0.13 $\mu{\rm m}$ CMOS |
| 148 | -- | 156 | Shih-Fu Liu, Pedro Reviriego, Juan Antonio Maestro. Efficient Majority Logic Fault Detection With Difference-Set Codes for Memory Applications |
| 157 | -- | 161 | Faiz-ul Hassan, Wim Vanderbauwhede, Fernando Rodríguez Salazar. Impact of Random Dopant Fluctuations on the Timing Characteristics of Flip-Flops |
| 162 | -- | 166 | M. Costagliola, D. de Caro, Antonio Girardi, Roberto Izzi, N. Rinaldi, M. Spirito, P. Spirito. An Experimental Power-Lines Model for Digital ASICs Based on Transmission Lines |
| 167 | -- | 171 | Tung-Hua Yeh, Sying-Jyan Wang. Power-Aware High-Level Synthesis With Clock Skew Management |
| 172 | -- | 176 | Irith Pomeranz, Sudhakar M. Reddy. Resolution of Diagnosis Based on Transition Faults |
| 176 | -- | 181 | Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki. Robust Secure Scan Design Against Scan-Based Differential Cryptanalysis |
| 181 | -- | 186 | Jisu Kim, Kyungho Ryu, Seung-Hyuk Kang, Seong-Ook Jung. A Novel Sensing Circuit for Deep Submicron Spin Transfer Torque MRAM (STT-MRAM) |
| 186 | -- | 191 | Xiaoxia Wu, Wei Zhao, Mark Nakamoto, Chandra Nimmagadda, Durodami Lisk, Sam Gu, Riko Radojcic, Matt Nowak, Yuan Xie. Electrical Characterization for Intertier Connections and Timing Analysis for 3-D ICs |
| 191 | -- | 196 | Andrew B. Kahng, Bin Li, Li-Shiuan Peh, Kambiz Samadi. ORION 2.0: A Power-Area Simulator for Interconnection Networks |