The following publications are possibly variants of this publication:
- Test Scheduling for Wafer-Level Test-During-Burn-In of Core-Based SoCsSudarshan Bahukudumbi, Krishnendu Chakrabarty, Richard Kacprowicz. date 2008: 1103-1106 [doi]
- Test-Length and TAM Optimization for Wafer-Level Reduced Pin-Count Testing of Core-Based SoCsSudarshan Bahukudumbi, Krishnendu Chakrabarty. tcad, 28(1):111-120, 2009. [doi]
- Test-Length Selection and TAM Optimization for Wafer-Level, Reduced Pin-Count Testing of Core-Based Digital SoCsSudarshan Bahukudumbi, Krishnendu Chakrabarty. vlsid 2007: 459-464 [doi]
- Recent Advances in Test Planning for Modular Testing of Core-Based SOCsVikram Iyengar, Krishnendu Chakrabarty, Erik Jan Marinissen. ats 2002: 320 [doi]
- Test planning for modular testing of hierarchical SOCsKrishnendu Chakrabarty, Vikram Iyengar, Mark D. Krasniewski. tcad, 24(3):435-448, 2005. [doi]
- A Set of Benchmarks fo Modular Testing of SOCsErik Jan Marinissen, Vikram Iyengar, Krishnendu Chakrabarty. itc 2002: 519-528 [doi]
- Defect-Oriented and Time-Constrained Wafer-Level Test-Length Selection for Core-Based Digital SoCsSudarshan Bahukudumbi, Krishnendu Chakrabarty. itc 2006: 1-10 [doi]