The following publications are possibly variants of this publication:
- Anomalous latchup failure induced by on-chip ESD protection circuit in a high-voltage CMOS IC productI-Cheng Lin, Chih-Yao Huang, Chuan-Jane Chao, Ming-Dou Ker. mr, 43(8):1295-1301, 2003. [doi]
- ESD protection design for IC with power-down-mode operationMing-Dou Ker, Kun-Hsien Lin. iscas 2004: 717-720
- Latchup-free ESD protection design with complementary substrate-triggered SCR devicesMing-Dou Ker, Kuo-Chun Hsu. jssc, 38(8):1380-1392, 2003. [doi]
- ESD Protection Design for Mixed-Voltage I/O Circuit with Substrate-Triggered Technique in Sub-Quarter-Micron CMOS ProcessMing-Dou Ker, Chien-Hui Chuang, Kuo-Chun Hsu, Wen-Yu Lo. isqed 2002: 331-336 [doi]
- ESD protection design for I/O cells in sub-130-nm CMOS technology with embedded SCR structureKun-Hsien Lin, Ming-Dou Ker. iscas 2005: 1182-1185 [doi]
- Low-capacitance ESD protection design for high-speed I/O interfaces in a 130-nm CMOS processYuan-Wen Hsiao, Ming-Dou Ker. mr, 49(6):650-659, 2009. [doi]
- Low-Voltage-Triggered PNP Devices for ESD Protection Design in Mixed-Voltage I/O Interface with Over-VDD and Under-VSS Signal LevelsMing-Dou Ker, Wei-Jen Chang, Wen-Yu Lo. isqed 2004: 433-438 [doi]