2 28-nm pseudo 2-read/write dual-port SRAM using double pumping circuitry - researchr publication related

researchr

You are not signed in
Sign in
Sign up

Yuichiro Ishii, Makoto Yabuuchi, Yohei Sawada, Masao Morimoto, Yasumasa Tsukamoto, Yuta Yoshida, Ken Shibata, Toshiaki Sano, Shinji Tanaka, Koji Nii. 2 28-nm pseudo 2-read/write dual-port SRAM using double pumping circuitry. In IEEE Asian Solid-State Circuits Conference, A-SSCC 2016, Toyama, Japan, November 7-9, 2016. pages 17-20, IEEE, 2016. [doi]

The following publications are possibly variants of this publication:

A 512-kb 1-GHz 28-nm partially write-assisted dual-port SRAM with self-adjustable negative bias bitlineShinji Tanaka, Yuichiro Ishii, Makoto Yabuuchi, Toshiaki Sano, Koji Tanaka, Yasumasa Tsukamoto, Koji Nii, Hirotoshi Sato. vlsic 2014: 1-2 [doi]

A 28-nm 1R1W Two-Port 8T SRAM Macro With Screening Circuitry Against Read Disturbance and Wordline Coupling Noise FailuresMakoto Yabuuchi, Yasumasa Tsukamoto, Hidehiro Fujiwara, Miki Tanaka, Shinji Shinji, Koji Nii. tvlsi, 26(11):2335-2344, 2018. [doi]

A 28 nm Dual-Port SRAM Macro With Screening Circuitry Against Write-Read Disturb Failure IssuesYuichiro Ishii, Hidehiro Fujiwara, Shinji Tanaka, Yasumasa Tsukamoto, Koji Nii, Yuji Kihara, K. Yanagisawa. jssc, 46(11):2535-2544, 2011. [doi]

2 16-nm FinFET double pumping 1W1R 2-port SRAM with 313 ps read access timeMakoto Yabuuchi, Yohei Sawada, Toshiaki Sano, Yuichiro Ishii, Shinji Tanaka, Miki Tanaka, Koji Nii. vlsic 2016: 1-2 [doi]

runs on WebDSL