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Moo-young Kim, Dongsuk Shin, Hyunsoo Chae, Chulwoo Kim. A Low-Jitter Open-Loop All-Digital Clock Generator With Two-Cycle Lock-Time. IEEE Trans. VLSI Syst., 17(10):1461-1469, 2009. [doi]
Possibly Related PublicationsThe following publications are possibly variants of this publication: A Low-Jitter Open-Loop All-Digital Clock Generator with 2 Cycle Lock-TimeMoo-young Kim, Dongsuk Shin, Hyunsoo Chae, Sunghwa Ok, Chulwoo Kim. cicc 2007: 369-372 [doi] Layout Synthesis and Loop Parameter Optimization of a Low-Jitter All-Digital Pixel Clock GeneratorWooseok Kim, Jaejin Park, Hojin Park, Deog Kyoon Jeong. jssc, 49(3):657-672, 2014. [doi]
The following publications are possibly variants of this publication: