The following publications are possibly variants of this publication:
- On Maximizing the Fault Coverage for a Given Test Length Limit in a Synchronous Sequential CircuitIrith Pomeranz, Sudhakar M. Reddy. TC, 53(9):1121-1133, 2004. [doi]
- Test sequences to achieve high defect coverage for synchronous sequential circuitsIrith Pomeranz, Sudhakar M. Reddy. tcad, 17(10):1017-1029, 1998. [doi]
- On Maximizing the Fault Coverage for a Given Test Length Limit in a Synchronous Sequential CircuitIrith Pomeranz, Sudhakar M. Reddy. vts 2003: 173-178 [doi]
- EXTEST: a method to extend test sequences of synchronous sequential circuits to increase the fault coverageIrith Pomeranz, Sudhakar M. Reddy. vts 1997: 329-335 [doi]
- Increasing Fault Coverage for Synchronous Sequential Circuits by the Multiple Observation Time Test StrategyIrith Pomeranz, Sudhakar M. Reddy, Lakshmi N. Reddy. iccad 1991: 454-457
- TEMPLATES: A Test Generation Procedure for Synchronous Sequential CircuitsIrith Pomeranz, Sudhakar M. Reddy. ats 1997: 74 [doi]
- Built-in test generation for synchronous sequential circuitsIrith Pomeranz, Sudhakar M. Reddy. iccad 1997: 421-426 [doi]
- On the Use of Functional Test Generation in Diagnostic Test Generation for Synchronous Sequential CircuitsIrith Pomeranz, Sudhakar M. Reddy. ENTCS, 174(4):83-93, 2007. [doi]