The following publications are possibly variants of this publication:
- Logic BIST With Capture-Per-Clock Hybrid Test PointsElham K. Moghaddam, Nilanjan Mukherjee 0001, Janusz Rajski, Jedrzej Solecki, Jerzy Tyszer, Justyna Zawada. tcad, 38(6):1028-1041, 2019. [doi]
- Staggered ATPG with capture-per-cycle observation test pointsYingdi Liu, Janusz Rajski, Sudhakar M. Reddy, Jedrzej Solecki, Jerzy Tyszer. vts 2018: 1-6 [doi]
- Test point insertion in hybrid test compression/LBIST architecturesElham K. Moghaddam, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer, Justyna Zawada. itc 2016: 1-10 [doi]