The following publications are possibly variants of this publication:
- A controller redesign technique to enhance testability of controller-data path circuitsSujit Dey, Vijay Gangaram, Miodrag Potkonjak. tcad, 17(2):157-168, 1998. [doi]
- Controller Resynthesis for Testability Enhancement of RTL Controller/Data Path CircuitsSrivaths Ravi, Indradeep Ghosh, Rabindra K. Roy, Sujit Dey. et, 13(2):201-212, 1998. [doi]
- Controller Resynthesis for Testability Enhancement of RTL Controller/Data path CircuitsSrivaths Ravi, Indradeep Ghosh, Rabindra K. Roy, Sujit Dey. vlsid 1998: 193-198 [doi]
- A controller-based design-for-testability technique for controller-data path circuitsSujit Dey, Vijay Gangaram, Miodrag Potkonjak. iccad 1995: 534-540 [doi]
- Behavioral Synthesis for Hierarchical Testability of Controller/Data Path Circuits with Conditional BranchesSandeep Bhatia, Niraj K. Jha. iccd 1994: 91-96
- Integration of hierarchical test generation with behavioral synthesis of controller and data path circuitsSandeep Bhatia, Niraj K. Jha. tvlsi, 6(4):608-619, 1998. [doi]