The following publications are possibly variants of this publication:
- Correction to "A Linearized, Low Phase Noise VCO Based 25 GHz PLL With Autonomic Biasing"Bodhisatwa Sadhu, Mark A. Ferriss, Arun S. Natarajan 0001, Soner Yaldiz, Jean-Olivier Plouchart, Alexander V. Rylyakov, Alberto Valdes-Garcia, Benjamin D. Parker, Aydin Babakhani, Scott K. Reynolds, Xin Li 0001, Lawrence T. Pillage, Ramesh Harjani, José A. Tierno, Daniel J. Friedman. jssc, 48(6):1539, June 2013. [doi]
- A 23.5 GHz PLL With an Adaptively Biased VCO in 32 nm SOI-CMOSJean-Olivier Plouchart, Mark A. Ferriss, A. S. Natarajan, Alberto Valdes-Garcia, Bodhisatwa Sadhu, Alexander Rylyakov, Benjamin D. Parker, Michael P. Beakes, Aydin Babakhani, Soner Yaldiz, Larry T. Pileggi, Ramesh Harjani, Scott K. Reynolds, José A. Tierno, Daniel J. Friedman. tcas, 60-I(8):2009-2017, 2013. [doi]
- A 23.5GHz PLL with an adaptively biased VCO in 32nm SOI-CMOSJean-Olivier Plouchart, Mark A. Ferriss, Arun Natarajan, Alberto Valdes-Garcia, Bodhisatwa Sadhu, Alexander Rylyakov, Benjamin D. Parker, Michael P. Beakes, Aydin Babakhani, Soner Yaldiz, Lawrence T. Pileggi, Ramesh Harjani, Scott K. Reynolds, José A. Tierno, Daniel J. Friedman. cicc 2012: 1-4 [doi]