The following publications are possibly variants of this publication:
- Modeling sequential circuits with shared structurally synthesized BDDsRaimund Ubar, Mihhail Marenkov, Dmitri Mironov, Vladimir Viies. idt 2014: 130-135 [doi]
- Shared Structurally Synthesized BDDs for speeding-up parallel pattern simulation in digital circuitsRaimund Ubar, Lembit Jurimagi, Jaan Raik. norchip 2015: 1-4 [doi]
- Structurally synthesized multiple input BDDs for simulation of digital circuitsRaimund Ubar, Dmitri Mironov, Jaan Raik, Artur Jutman. icecsys 2009: 451-454 [doi]
- Logic simulation and fault collapsing with shared structurally synthesized bddsDmitri Mironov, Raimund Ubar, Jaan Raik. ets 2014: 1-2 [doi]
- Lower bounds of the size of Shared Structurally Synthesized BDDsRaimund Ubar, Dmitri Mironov. ddecs 2014: 77-82 [doi]
- Structurally Synthesized Multiple Input BDDs for Speeding Up Logic-Level Simulation of Digital CircuitsDmitri Mironov, Raimund Ubar, Sergei Devadze, Jaan Raik, Artur Jutman. dsd 2010: 658-663 [doi]
- Fault Simulation with Parallel Critical Path Tracing for Combinatorial Circuits Using Structurally Synthesized BDDsSergei Devadze, Jaan Raik, Artur Jutman, Raimund Ubar. latw 2006: 97-102
- True Path Tracing in Structurally Synthesized BDDs for Testability Analysis of Digital CircuitsRaimund Ubar, Lembit Jürimägi, Adeniyi Olanrewaju Adekoya, Maksim Jenihhin. dsd 2019: 492-499 [doi]
- Calculation of probabilistic testability measures for digital circuits with Structurally Synthesized BDDsLembit Jürimägi, Raimund Ubar, Maksim Jenihhin, Jaan Raik. mam, 77:103117, 2020. [doi]
- Efficient Single-Pattern Fault Simulation on Structurally Synthesized BDDsJaan Raik, Raimund Ubar, Sergei Devadze, Artur Jutman. edcc 2005: 332-344 [doi]