The following publications are possibly variants of this publication:
- Design of power-rail ESD clamp circuit with adjustable holding voltage against mis-trigger or transient-induced latch-on eventsChih-Ting Yeh, Yung-Chih Liang, Ming-Dou Ker. iscas 2011: 1403-1406 [doi]
- PMOS-based power-rail ESD clamp circuit with adjustable holding voltage controlled by ESD detection circuitChih-Ting Yeh, Ming-Dou Ker. mr, 53(2):208-214, 2013. [doi]
- Overview on ESD protection design for mixed-voltage I/O interfaces with high-voltage-tolerant power-rail ESD clamp circuits in low-voltage thin-oxide CMOS technologyMing-Dou Ker, Wei-Jen Chang. mr, 47(1):27-35, 2007. [doi]
- On the Design of Power-rail ESD Clamp Circuit with Consideration of Gate Leakage Current in 65-nm Low-voltage CMOS ProcessMing-Dou Ker, Po-Yen Chiu, Fu-Yi Tsai, Yeong-Jar Chang. iscas 2009: 2281-2284 [doi]
- The impact of low-holding-voltage issue in high-voltage CMOS technology and the design of latchup-free power-rail ESD clamp circuit for LCD driver ICsMing-Dou Ker, Kun-Hsien Lin. jssc, 40(8):1751-1759, 2005. [doi]
- Investigation and Design of On-Chip Power-Rail ESD Clamp Circuits Without Suffering Latchup-Like Failure During System-Level ESD TestMing-Dou Ker, Cheng-Cheng Yen. jssc, 43(11):2533-2545, 2008. [doi]
- Design on the turn-on efficient power-rail ESD clamp circuit with stacked polysilicon diodesMing-Dou Ker, Tung-Yang Chen. iscas 2001: 758-761 [doi]
- Novel cascode NCLSCR/PCLSCR design with tunable holding voltage for safe whole-chip ESD protectionMing-Dou Ker, Hun-Hsien Chang. cicc 1998: 541-544 [doi]
- Area-Efficient ESD-Transient Detection Circuit With Smaller Capacitance for On-Chip Power-Rail ESD Protection in CMOS ICsShih-Hung Chen, Ming-Dou Ker. tcas, 56-II(5):359-363, 2009. [doi]
- Design on Power-Rail ESD Clamp Circuit for 3.3-V I/O Interface by Using Only 1-V/2.5-V Low-Voltage Devices in a 130-nm CMOS ProcessMing-Dou Ker, Wen-Yi Chen, Kuo-Chun Hsu. tcas, 53(10):2187-2193, 2006. [doi]