Abstract is missing.
- Open-Source EDA: If We Build It, Who Will Come?Andrew B. Kahng. 1-6 [doi]
- Scalable Open-Source System-on-Chip Design: (Invited Talk - Extended Abstract)Luca P. Carloni. 7-9 [doi]
- Multi-label HD Classification in 3D FlashJustin Morris, Yilun Hao, Saransh Gupta, Ranganathan Ramkumar, Jeffrey Yu, Mohsen Imani, Baris Aksanli, Tajana Rosing. 10-15 [doi]
- Early RTL Analysis for SCA Vulnerability in Fuzzy Extractors of Memory-Based PUF Enabled DevicesXinhui Lai, Maksim Jenihhin, Georgios N. Selimis, Sven Goossens, Roel Maes, Kolin Paul. 16-21 [doi]
- SAT-Based Data-Flow Mapping Onto Array ProcessorYukio Miyasaka, Masahiro Fujita. 22-27 [doi]
- abstractPIM: Bridging the Gap Between Processing-In-Memory Technology and Instruction Set ArchitectureAdi Eliahu, Rotem Ben Hur, Ronny Ronen, Shahar Kvatinsky. 28-33 [doi]
- Layout Considerations of Logic Designs Using an N-layer 3D Nanofabric Process FlowEdouard Giacomin, Jürgen Bömmels, Julien Ryckaert, Francky Catthoor, Pierre-Emmanuel Gaillardon. 34-39 [doi]
- Simultaneous Estimation of Temperature and Voltage from Digital Delay DiversityXiaoyu Lian, Sherief Reda, Jacob K. Rosenstein. 40-45 [doi]
- Exploring the FPGA Implementations of the LBlock, Piccolo, Twine, and Klein CiphersS. Moraitis, D. Seitanidis, George Theodoridis, Odysseas G. Koufopavlou. 46-51 [doi]
- A 0.8V 875 MS/s 7b low-power SAR ADC for ADC-Based Wireline Receivers in 22nm FDSOIDavid Cordova, Wim Cops, Yann Deval, Francois Rivet, Hervé Lapuyade, Nicolas Nodenot, Yohan Piccin. 52-57 [doi]
- Cross-Layer Hardware/Software Assessment of the Open-Source NVDLA Configurable Deep Learning AcceleratorAlessandro Veronesi, Milos Krstic, Davide Bertozzi. 58-63 [doi]
- X-MAGIC: Enhancing PIM Using Input Overwriting CapabilitiesNatan Peled, Rotem Ben Hur, Ronny Ronen, Shahar Kvatinsky. 64-69 [doi]
- A Minimalistic Perspective on Koblitz Curve Scalar Multiplication for FPGA PlatformsSiddhartha Chowdhury, Debapriya Basu Roy, Debdeep Mukhopadhyay. 70-75 [doi]
- 3D Logic Cells Design and Results Based on Vertical NWFET Technology Including Tied Compact ModelChhandak Mukherjee, Marina Deng, François Marc, Cristell Maneux, Arnaud Poittevin, Ian O'Connor, Sébastien Le Beux, Cédric Marchand 0002, Abhishek Kumar, Aurélie Lecestre, Guilhem Larrieu. 76-81 [doi]
- Automatic Timing Closure for Relative Timed DesignsTannu Sharma, Kenneth S. Stevens. 82-87 [doi]
- Mining Hyperproperties from Behavioral TracesMayank Rawat, Sujit Kumar Muduli, Pramod Subramanyan. 88-93 [doi]
- A Hybrid Cache HW/SW Stack for Optimizing Neural Network Runtime, Power and EnduranceWilliam Andrew Simon, Alexandre Levisse, Marina Zapater, David Atienza. 94-99 [doi]
- An ULP Self-Supplied Brain Interface CircuitAmin Aghighi, Massood Tabib-Azar, Armin Tajalli. 100-104 [doi]
- Energy and Area Efficient Mixed-Mode MCMC MIMO DetectorAmin Aghighi, Behrouz Farhang-Boroujeny, Armin Tajalli. 105-110 [doi]
- MIST: monitor generation from informal specifications for firmware verificationSamuele Germiniani, Moreno Bragaglio, Graziano Pravadelli. 111-116 [doi]
- Breaking ACORN at Bitstream LevelMichail Moraitis, Elena Dubrova, Kalle Ngo. 117-122 [doi]
- Breaking Barriers: Maximizing Array Utilization for Compute in-Memory FabricsBrian Crafton, Samuel Spetalnick, Gauthaman Murali, Tushar Krishna, Sung Kyu Lim, Arijit Raychowdhury. 123-128 [doi]
- SANSCrypt: A Sporadic-Authentication-Based Sequential Logic Encryption SchemeYinghua Hu, Kaixin Yang, Shahin Nazarian, Pierluigi Nuzzo. 129-134 [doi]
- Basic Block Encoding Based Run-time CFI Check for Embedded SoftwareLove Kumar Sah, Srivarsha Polnati, Sheikh Ariful Islam, Srinivas Katkoori. 135-140 [doi]
- An Open-source Framework for Autonomous SoC Design with Analog Block GenerationTutu Ajayi, Sumanth Kamineni, Yaswanth K. Cherivirala, Morteza Fayazi, Kyumin Kwon, Mehdi Saligane, Shourya Gupta, Chien-Hen Chen, Dennis Sylvester, David T. Blaauw, Ronald G. Dreslinski, Benton H. Calhoun, David D. Wentzloff. 141-146 [doi]
- Ultra-Compact, Scalable, Energy-Efficient $VO_{2}$ Insulator-Metal-Transition Oxide Based Spiking Neurons for Liquid State MachinesSamiran Ganguly, Nikhil Shukla, Avik W. Ghosh. 147-152 [doi]
- Testing the Divergence Stack Memory on GPGPUs: A Modular in-Field Test StrategyJosie E. Rodriguez Condia, Matteo Sonza Reorda. 153-158 [doi]
- A Model Study of Multilevel Signaling for High-Speed Chiplet-to-Chiplet Communication in 2.5D IntegrationRakshith Saligram, Ankit Kaul, Muhannad S. Bakir, Arijit Raychowdhury. 159-164 [doi]
- RAT: A Lightweight System-level Soft Error Mitigation TechniqueJonas Gava, Ricardo Augusto da Luz Reis, Luciano Ost. 165-170 [doi]
- A Low-Power 10 to 15 Gb/s Common-Gate CTLE Based on Optimized Active InductorsAmin Aghighi, Armin Tajalli, Mohammad Taherzadeh-Sani. 171-175 [doi]
- PT controlled buck converter with adaptive PCCM using charge monitoring and NMOS current sensingYongnan Chen, Yanhan Zeng, JunKai Chen, Hong-Zhou Tan. 176-180 [doi]
- Fast-transient, light-load efficient DC-DC converter using an auxiliary D-LDOHaochang Zhi, Yanhan Zeng, Wei Zhou, Hongzhou Tan. 181-185 [doi]
- Subthreshold-Hybrid Solutions for Thermal Sensor and Reference Circuits in Advanced CMOSMatthias Eberlein, Harald Pretl. 186-191 [doi]
- Temperature and Supply Voltage Monitoring with Current-mode Relaxation OscillatorsShanshan Dai, Caleb R. Tulloss, Xiaoyu Lian, Kangping Hu, Sherief Reda, Jacob K. Rosenstein. 192-197 [doi]
- Design, Implementation and Analysis of Efficient Hardware-Based Security PrimitivesN. Nalla Anandakumar, Somitra Kumar Sanadhya, Mohammad S. Hashmi. 198-199 [doi]
- Multiple-NoC Exploration and Customization for Energy Efficient Traffic DistributionSonal Yadav, Vijay Laxmi, Manoj Singh Gaur. 200-201 [doi]
- Design Automation for Side Channel Resistant Lightweight CryptographyRajat Sadhukhan, Debdeep Mukhopadhyay. 202-203 [doi]
- Optimization Tools for ConvNets on the EdgeValentino Peluso, Enrico Macii, Andrea Calimera. 204-205 [doi]
- Memory and Energy Efficient Method Toward Sparse Neural Network Using LFSR IndexingForoozan Karimzadeh, Arijit Raychowdhury. 206-207 [doi]
- Online Reward-Based Training of Spiking Central Pattern Generator for Hexapod LocomotionAshwin Sanjay Lele, Yan Fang, Justin Ting, Arijit Raychowdhury. 208-209 [doi]
- Device Modeling and Circuit Design for Scalable Beyond-CMOS ComputingXuan Hu, Naimul Hassan, Wesley H. Brigner, Maverick Chauwin, Joseph S. Friedman. 210-211 [doi]