Abstract is missing.
- Algorithm to Architecture to RTL to GDSII: Incorporating Security into All Phases of SoC Design and Implementation Flow - KeynoteSerge Leef. [doi]
- Edge Computing Trends, Design and Test Challenges - KeynoteKarim Arabi. [doi]
- Identifying Good-Dice-in-Bad-Neighborhoods Using Artificial Neural NetworksCheng-Hao Yang, Chia-Heng Yen, Ting-Rui Wang, Chun-Teng Chen, Mason Chern, Ying-Yen Chen, Jih-Nung Lee, Shu-Yi Kao, Kai-Chiang Wu, Mango Chia-Tso Chao. 1-7 [doi]
- Compact Set of LFSR Seeds for Diagnostic TestsIrith Pomeranz. 1-7 [doi]
- Special Session: Noisy Intermediate-Scale Quantum (NISQ) Computers - How They Work, How They Fail, How to Test Them?Sebastian Brandhofer, Simon J. Devitt, Thomas Wellens, Ilia Polian. 1-10 [doi]
- Combining Architectural Simulation and Software Fault Injection for a Fast and Accurate CNNs Reliability Evaluation on GPUsJosie E. Rodriguez Condia, Fernando Fernandes dos Santos, Matteo Sonza Reorda, Paolo Rech. 1-7 [doi]
- Unsupervised Root-Cause Analysis with Transfer Learning for Integrated SystemsRenjian Pan, Xin Li 0001, Krishnendu Chakrabarty. 1-6 [doi]
- New Techniques for the Automatic Identification of Uncontrollable Lines in a CPU CoreNikolaos I. Deligiannis, Riccardo Cantoro, Matthias Sauer 0002, Bernd Becker 0001, Matteo Sonza Reorda. 1-7 [doi]
- TSV Fault Modeling and A BIST Solution for TSV Pre-bond TestKangkang Xu, Yang Yu, Xiyuan Peng. 1-6 [doi]
- Design for Testability of Low Dropout RegulatorsAnurag Tulsiram, William R. Eisenstadt. 1-7 [doi]
- Special Session: Operating Systems under test: an overview of the significance of the operating system in the resiliency of the computing continuumEmmanuel Casseau, Petr Dobiás, Oliver Sinnen, Gennaro Severino Rodrigues, Fernanda Lima Kastensmidt, Alessandro Savino, Stefano Di Carlo, Maurizio Rebaudengo, Alberto Bosio. 1-10 [doi]
- Memory-Efficient Adaptive Test Pattern Reordering for Accurate DiagnosisChenlei Fang, Qicheng Huang, R. D. Shawn Blanton. 1-7 [doi]
- On the Reliability of In-Memory Computing: Impact of Temperature on Ferroelectric TCAMSimon Thomann, Chao Li, Cheng Zhuo, Om Prakash 0007, Xunzhao Yin, Xiaobo Sharon Hu, Hussam Amrouch. 1-6 [doi]
- A Hybrid Protection Scheme for Reconfigurable Scan NetworksNatalia Lylina, Ahmed Atteya, Hans-Joachim Wunderlich. 1-7 [doi]
- Special Session: CAD for Hardware Security - Automation is Key to Adoption of SolutionsSohrab Aftabjahani, Ryan Kastner, Mark Mohammad Tehranipoor, Farimah Farahmandi, Jason Oberg, Anders Nordstrom, Nicole Fern, Alric Althoff. 1-10 [doi]
- Special Session: Machine Learning for Semiconductor Test and ReliabilityHussam Amrouch, Animesh Basak Chowdhury, Wentian Jin, Ramesh Karri, Farshad Khorrami, Prashanth Krishnamurthy, Ilia Polian, Victor M. van Santen, Benjamin Tan, Sheldon X.-D. Tan. 1-11 [doi]
- Transistor Self-Heating: The Rising Challenge for Semiconductor TestingOm Prakash 0007, Chetan K. Dabhi, Yogesh Singh Chauhan, Hussam Amrouch. 1-7 [doi]
- Defect Characterization and Testing of Skyrmion-Based Logic CircuitsZiqi Zhou, Ujjwal Guin, Peng Li, Vishwani D. Agrawal. 1-7 [doi]
- Hybrid Methodology for Verification of SW Safety MechanismsSarvesh Patankar, Sainath Karlapalem, Sakshi Biyani, Wen Chen, Roman Chovanec, Martin Vlk, Martin Kaspar. 1-4 [doi]
- Reliability Evaluation of the Count Min Sketch (CMS) against Single Event Transients (SETs)Jinhua Zhu, Zhen Gao, Jie Jin, Pedro Reviriego. 1-6 [doi]
- Reliability-Driven Voltage Optimization for NCFET-based SRAM Memory BanksVictor M. van Santen, Simon Thomann, Yogesh S. Chauchan, Jörg Henkel, Hussam Amrouch. 1-7 [doi]
- Automated Observability Analysis for Mixed-Signal CircuitsStephen Sunter, Krzysztof Jurga. 1-6 [doi]
- Special Session - Test for AI Chips: from DFT to On-line TestingHuawei Li, Xiaowei Li, Yu Huang 0005, Ying Wang, Gary Guo. 1 [doi]
- GATPS: An attention-based graph neural network for predicting SDC-causing instructionsJunchi Ma, Zongtao Duan, Lei Tang 0002. 1-7 [doi]
- Special Session - Machine Learning in Test: A Survey of Analog, Digital, Memory, and RF Integrated CircuitsSoham Roy, Spencer K. Millican, Vishwani D. Agrawal. 1-14 [doi]
- On Workload-Aware DRAM Failure Prediction in Large-Scale Data CentersXingyi Wang, Yu Li, Yiquan Chen, Shiwen Wang, Yin Du, Cheng He, Yuzhong Zhang, Pinan Chen, Xin Li, Wenjun Song, Qiang Xu, Li Jiang 0002. 1-6 [doi]
- Special Session: Reliability Analysis for AI/ML HardwareShamik Kundu, Kanad Basu, Mehdi Sadi, Twisha Titirsha, Shihao Song, Anup Das 0001, Ujjwal Guin. 1-10 [doi]
- Special Session: Physical Attacks through the Chip Backside: Threats, Challenges, and OpportunitiesElham Amini, Kai Bartels, Christian Boit, Marius Eggert, Norbert Herfurth, Tuba Kiyan, Thilo Krachenfels, Jean-Pierre Seifert, Shahin Tajik. 1-12 [doi]
- Maintaining NIST-Traceability for MEMS Sensors via In-Field Electrical RecalibrationIshaan Bassi, Sule Ozev, Doohwang Chang. 1-7 [doi]
- Timing Critical Path Validation for Intel ATOM Cores Using Structural TestWei Li, Shih-yu Yang, Khen Wee, Ricardo Sanchez, Jay Desai, Kun-Han Tsai, Xijiang Lin. 1-6 [doi]
- Multi-Bit Blinding: A Countermeasure for RSA Against Side Channel AttacksAbdullah Aljuffri, Cezar Reinbrecht, Said Hamdioui, Mottaqiallah Taouil. 1-6 [doi]
- An Energy-Efficient Approximate Systolic Array Based on Timing Error Prediction and PreventionNing-Chi Huang, Wei-Kai Tseng, Huan-Jan Chou, Kai-Chiang Wu. 1-7 [doi]
- Enabling ECC and Repair Features in an eFuse Box for Memory Repair ApplicationsSrikanth Beerla, Miguel Costa. 1-4 [doi]
- Trim Time Reduction in Analog/RF ICs Based on Inter-Trim CorrelationV. A. Niranjan, Deepika Neethirajan, Constantinos Xanthopoulos, E. De la Rosa, C. Alleyne, S. Mier, Yiorgos Makris. 1-7 [doi]
- Two Pattern Timing Tests Capturing Defect-Induced Multi-Gate Delay Impact of ShortsSujay Pandey, Zhiwei Liao, Shreyas Nandi, Suriyaprakash Natarajan, Arani Sinha, Adit D. Singh, Abhijit Chatterjee. 1-7 [doi]
- Deep Stalling using a Coverage Driven Genetic Algorithm FrameworkSiddhanth Dhodhi, Debarshi Chatterjee, Eric Hill, Saad Godil. 1-4 [doi]
- SAIF: Automated Asset Identification for Security Verification at the Register Transfer LevelNusrat Farzana, Avinash Ayalasomayajula, Fahim Rahman, Farimah Farahmandi, Mark Mohammad Tehranipoor. 1-7 [doi]