Carl Radens - researchr alias

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Viewing Publication 1 - 7 from 7

2019

An Extrinsic Device and Leakage Mechanism in Advanced Bulk FinFET SRAMRandy W. Mann, Meixiong Zhao, Sanjay Parihar, Qun Gao, Ankur Arya, Carl Radens, Shesh Mani Pandey, Joseph Versaggi, Jack M. Higman, Rick Carter. tvlsi, 27(8):1819-1827, 2019. [doi]

2016

A Universal Hardware-Driven PVT and Layout-Aware Predictive Failure Analytics for SRAMRajiv V. Joshi, Sudesh Saroop, Rouwaida Kanj, Yang Liu, Weike Wang, Carl Radens, Yue Tan, Karthik Yogendra. tvlsi, 24(3):968-978, 2016. [doi]

2015

Super Fast Physics-Based Methodology for Accurate Memory Yield PredictionRajiv V. Joshi, Keunwoo Kim, Rouwaida Kanj, Ajay N. Bhoj, Matthew M. Ziegler, Phil Oldiges, Pranita Kerber, Robert Wong, Terence Hook, Sudesh Saroop, Carl Radens, Chun-Chen Yeh. tvlsi, 23(3):534-543, 2015. [doi]

2012

A 64 Mb SRAM in 32 nm High-k Metal-Gate SOI Technology With 0.7 V Operation Enabled by Stability, Write-Ability and Read-Ability EnhancementsHarold Pilo, Igor Arsovski, Kevin Batson, Geordie Braceras, John Gabric, Robert M. Houle, Steve Lamphier, Carl Radens, Adnan Seferagic. jssc, 47(1):97-106, 2012. [doi]

2011

A 64Mb SRAM in 32nm High-k metal-gate SOI technology with 0.7V operation enabled by stability, write-ability and read-ability enhancementsHarold Pilo, Igor Arsovski, Kevin Batson, Geordie Braceras, John Gabric, Robert M. Houle, Steve Lamphier, Frank Pavlik, Adnan Seferagic, Liang-Yu Chen, Shang-Bin Ko, Carl Radens. isscc 2011: 254-256 [doi]

2008

A Sub-600-mV, Fluctuation Tolerant 65-nm CMOS SRAM Array With Dynamic Cell BiasingAzeez J. Bhavnagarwala, Stephen Kosonocky, Carl Radens, Yuen H. Chan, Kevin Stawiasz, Uma Srinivasan, Steven P. Kowalczyk, Matthew M. Ziegler. jssc, 43(4):946-955, 2008. [doi]

2000

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