Daisuke Ikebuchi - researchr alias

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Viewing Publication 1 - 13 from 13

2011

Design and Implementation Fine-grained Power Gating on Microprocessor Functional UnitsZhao Lei, Daisuke Ikebuchi, Kimiyoshi Usami, Mitaro Namiki, Masaaki Kondo, Hiroshi Nakamura, Hideharu Amano. ipsj, 4:182-192, 2011. [doi]

A Leakage Efficient Instruction TLB Design for Embedded ProcessorsZhao Lei, Hui Xu, Daisuke Ikebuchi, Tetsuya Sunata, Mitaro Namiki, Hideharu Amano. ieicet, 94-D(8):1565-1574, 2011. [doi]

Performance, Area, and Power Evaluations of Ultrafine-Grained Run-Time Power-Gating Routers for CMPsHiroki Matsutani, Michihiro Koibuchi, Daisuke Ikebuchi, Kimiyoshi Usami, Hiroshi Nakamura, Hideharu Amano. tcad, 30(4):520-533, 2011. [doi]

Cool Mega-Array: A highly energy efficient reconfigurable acceleratorNobuaki Ozaki, Yoshihiro Yasuda, Yoshiki Saito, Daisuke Ikebuchi, Masayuki Kimura, Hideharu Amano, Hiroshi Nakamura, Kimiyoshi Usami, Mitaro Namiki, Masaaki Kondo. fpt 2011: 1-8 [doi]

Cool Mega-Arrays: Ultralow-Power Reconfigurable Accelerator ChipsNobuaki Ozaki, Yoshihiro Yasuda, Mai Izawa, Yoshiki Saito, Daisuke Ikebuchi, Hideharu Amano, Hiroshi Nakamura, Kimiyoshi Usami, Mitaro Namiki, Masaaki Kondo. micro, 31(6):6-18, 2011. [doi]

On-chip detection methodology for break-even time of power gated function unitsKimiyoshi Usami, Yuya Goto, Kensaku Matsunaga, Satoshi Koyama, Daisuke Ikebuchi, Hideharu Amano, Hiroshi Nakamura. islped 2010: 241-246 [doi]

A Leakage Efficient Data TLB Design for Embedded ProcessorsLei Zhao, Hui Xu, Daisuke Ikebuchi, Tetsuya Sunata, Mitaro Namiki, Hideharu Amano. ieicet, 94-D(1):51-59, 2011. [doi]

2010

Geyser-1: a MIPS R3000 CPU core with fine-grained run-time power gatingDaisuke Ikebuchi, Naomi Seki, Yu Kojima, M. Kamata, Lei Zhao, Hideharu Amano, Toshiaki Shirai, Satoshi Koyama, Tatsunori Hashida, Y. Umahashi, Hiroki Masuda, Kimiyoshi Usami, Seidai Takeda, Hiroshi Nakamura, Mitaro Namiki, Masaaki Kondo. aspdac 2010: 369-370 [doi]

Reducing instruction TLB s leakage power consumption for embedded processorsZhao Lei, Hui Xu, Daisuke Ikebuchi, Hideharu Amano, Tetsuya Sunata, Mitaro Namiki. green 2010: 477-484 [doi]

Ultra Fine-Grained Run-Time Power Gating of On-chip Routers for CMPsHiroki Matsutani, Michihiro Koibuchi, Daisuke Ikebuchi, Kimiyoshi Usami, Hiroshi Nakamura, Hideharu Amano. nocs 2010: 61-68 [doi]

Adaptive power gating for function units in a microprocessorKimiyoshi Usami, Tatsunori Hashida, Satoshi Koyama, Tatsuya Yamamoto, Daisuke Ikebuchi, Hideharu Amano, Mitaro Namiki, Masaaki Kondo, Hiroshi Nakamura. isqed 2010: 29-37 [doi]

2008

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