Richard J. Eickemeyer - researchr alias

researchr

You are not signed in
Sign in
Sign up

Viewing Publication 1 - 19 from 19

2021

2015

2011

Abstraction and microarchitecture scaling in early-stage power modelingHans M. Jacobson, Alper Buyuktosunoglu, Pradip Bose, Emrah Acar, Richard J. Eickemeyer. hpca 2011: 394-405 [doi]

2008

An 8T-SRAM for Variability Tolerance and Low-Voltage Operation in High-Performance CachesLeland Chang, Robert K. Montoye, Yutaka Nakamura, Kevin Batson, Richard J. Eickemeyer, Robert H. Dennard, Wilfried Haensch, Damir Jamsek. jssc, 43(4):956-963, 2008. [doi]

2005

Characterization of simultaneous multithreading (SMT) efficiency in POWER5Harry M. Mathis, Alex E. Mericas, John D. McCalpin, Richard J. Eickemeyer, Steven R. Kunkel. ibmrd, 49(4-5):555-564, 2005. [doi]

POWER5 system microarchitectureBalaram Sinharoy, Ronald N. Kalla, Joel M. Tendler, Richard J. Eickemeyer, Jody B. Joyner. ibmrd, 49(4-5):505-522, 2005. [doi]

2000

A multithreaded PowerPC processor for commercial serversJohn M. Borkenhagen, Richard J. Eickemeyer, Ronald N. Kalla, Steven R. Kunkel. ibmrd, 44(6):885-898, 2000. [doi]

A performance methodology for commercial serversSteven R. Kunkel, Richard J. Eickemeyer, Mikko H. Lipasti, Timothy J. Mullins, Brian O Krafka, Harold Rosenberg, Steven P. Vanderwiel, Philip L. Vitale, Larry D. Whitley. ibmrd, 44(6):851-872, 2000. [doi]

1997

Evaluation of Multithreaded Processors and Thread-Switch PoliciesRichard J. Eickemeyer, Ross E. Johnson, Steven R. Kunkel, Beng-Hong Lim, Mark S. Squillante, Ching-Farn Eric Wu. ishpc 1997: 75-90

1996

Evaluation of Multithreaded Uniprocessors for Commercial Application EnvironmentsRichard J. Eickemeyer, Ross E. Johnson, Steven R. Kunkel, Mark S. Squillante, Shiafun Liu. isca 1996: 203-212 [doi]

1994

SCISM: A scalable compound instruction set machineStamatis Vassiliadis, Bart Blaner, Richard J. Eickemeyer. ibmrd, 38(1):59-78, 1994.

1993

A load-instruction unit for pipelined processorsRichard J. Eickemeyer, Stamatis Vassiliadis. ibmrd, 37(4):547-564, 1993.

1992

Interlock collapsing ALU for increased instruction-level parallelismNadeem Malik, Richard J. Eickemeyer, Stamatis Vassiliadis. euromicro 1992: 149-157 [doi]

Instruction-level parallelism from execution interlock collapsingNadeem Malik, Richard J. Eickemeyer, Stamatis Vassiliadis. sigarch, 20(4):38-43, 1992. [doi]

On the attributes of the SCISM organizationStamatis Vassiliadis, Bart Blaner, Richard J. Eickemeyer. sigarch, 20(4):44-53, 1992. [doi]

1988

Performance Evaluation of On-Chip Register and Cache OrganizationsRichard J. Eickemeyer, Janak H. Patel. isca 1988: 64-72

Performance Evaluation of Multiple Register Set Architectures and Cache MemoriesRichard J. Eickemeyer. PhD thesis, University of Illinois Urbana-Champaign, USA, 1988. [doi]

1987

Performance Evaluation of Multiple Register SetsRichard J. Eickemeyer, Janak H. Patel. isca 1987: 264-271

Sign in or sign up to see more results.

runs on WebDSL