Shinji Nishimura - researchr alias

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Viewing Publication 1 - 18 from 18

2014

A 25-Gb/s 2.2-W 65-nm CMOS Optical Transceiver Using a Power-Supply-Variation-Tolerant Analog Front End and Data-Format ConversionTakashi Takemoto, Hiroki Yamashita, Fumio Yuki, Noboru Masuda, Hidehiro Toyoda, Norio Chujo, Yong Lee, Shinji Tsuji, Shinji Nishimura. jssc, 49(2):471-485, 2014. [doi]

2013

Compact and power-efficient 100-Gbps CMOS-based transceiverTakashi Takemoto, Hiroki Yamashita, Fumio Yuki, Shinji Tsuji, Yong Lee, Koichiro Adachi, Kazunori Shinoda, Yasunobu Matsuoka, Toshiki Sugawara, Shinji Nishimura, Norio Chujo, Masaaki Nido, Kazuhiko Kurata, Junji Baba, Yoshinori Watanabe, Naoya Ikeda. ofc 2013: 1-3 [doi]

2012

2011

2010

A 25 Gb/s × 4-channel 74 mW/ch transimpedance amplifier in 65 nm CMOSTakashi Takemoto, Fumio Yuki, Hiroki Yamashita, Shinji Tsuji, Tatsuya Saito, Shinji Nishimura. cicc 2010: 1-4 [doi]

100GbE PHY and MAC layer implementationsHidehiro Toyoda, Goichi Ono, Shinji Nishimura. cm, 48(3), 2010. [doi]

2008

A 100 Gb/s and High-Reliable Physical-Layer Architecture for VSR and Backplane EthernetHidehiro Toyoda, Michitaka Okuno, Shinji Nishimura, Matsuaki Terada. icc 2008: 5417-5421 [doi]

Technologies to Save Power for Carrier Class Routers and SwitchesMasaki Yamada, Takeki Yazaki, Shinji Nishimura, Naoya Ikeda. saint 2008: 385-388 [doi]

2007

Basic Simulation Result of Inter System Handover for Cognitive RadioTakashi Ishikawa, Seishi Hanaoka, Mikio Kataoka, Masashi Yano, Shinji Nishimura. fgcn 2007: 270-273 [doi]

A 100-Gb/s-Physical-Layer Architecture for Higher-Speed Ethernet for VSR and Backplane ApplicationsHidehiro Toyoda, Shinji Nishimura, Michitaka Okuno, Matsuaki Terada. ieicet, 90-C(10):1957-1963, 2007. [doi]

2006

Cache-Based Network Processor Architecture: Evaluation with Real Network TrafficMichitaka Okuno, Shinji Nishimura, Shin-ichi Ishida, Hiroaki Nishi. ieicet, 89-C(11):1620-1628, 2006. [doi]

100-Gb/s Physical-Layer Architecture for Next-Generation EthernetHidehiro Toyoda, Shinji Nishimura, Michitaka Okuno, Kouji Fukuda, Kouji Nakahara, Hiroaki Nishi. ieicet, 89-B(3):696-703, 2006. [doi]

2005

A 100-Gb-Ethernet subsystem for next-generation metro-area networkHidehiro Toyoda, Shinji Nishimura, Michitaka Okuno, Ryouji Yamaoka, Hiroaki Nishi. icc 2005: 1036-1042 [doi]

2001

RHiNET-3/SW: an 80-Gbit/s high-speed network switch for distributed parallel computingShinji Nishimura, Tomohiro Kudoh, Hiroaki Nishi, Junji Yamamoto, R. Ueno, Katsuyoshi Harasawa, Shuji Fukuda, Yasutaka Shikichi, Shigeto Akutsu, Koji Tasho, Hideharu Amano. hoti 2001: 119-123 [doi]

2000

RHiNET-2/SW a Hight-throughput, Compact Network-switch Using 8.8-Gbit/s Optical InterconnectionShinji Nishimura, K. Harasawa, N. Matsudaira, S. Akutsu, Tomohiro Kudoh, Hiroaki Nishi, Hideharu Amano. ngc, 18(2):187, 2000.

1991

Single board video codec for ISDN visual telephoneTetsuo Tajiri, Yutaka Suzuki, Shinji Nishimura, Hiroshi Yoshimura. icassp 1991: 2853-2856 [doi]

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