Tsuneo Nakata - researchr alias

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Viewing Publication 1 - 16 from 16

2021

Data Traffic Offloading and Rate Control for Vehicles Using Radio Environment, Network Load and Route PlanningTakeo Ohseki, Kosuke Yamazaki, Daiki Maemoto, Shigeki Kawai, Tsuneo Nakata, Akira Itou. pimrc 2021: 1463-1468 [doi]

2016

Precise Location by Fingerprinting Road Segments with Variation of Broadcast Wave ReceptionYuji Kamiya, Toru Nagura, Shigeki Kawai, Tsuneo Nakata. ieicet, 99-A(7):1465-1472, 2016. [doi]

2014

Precise Location by Fingerprinting Road Segments with Variation of Wireless ReceptionTsuneo Nakata, Shigeki Kawai. vtc 2014: 1-5 [doi]

2005

Integrating UML into SoC Design ProcessQiang Zhu, Ryosuke Oishi, Takashi Hasegawa, Tsuneo Nakata. date 2005: 836-837 [doi]

2004

System-on-chip validation using UML and CWLQiang Zhu, Ryosuke Oishi, Takashi Hasegawa, Tsuneo Nakata. codes 2004: 92-97 [doi]

System-on-Chip Verification Process Using UMLQiang Zhu, Tsuneo Nakata, Masataka Mine, Kenichiro Kuroki, Yoichi Endo, Takashi Hasegawa. uml 2005: 138-149 [doi]

2003

Multi-event algorithms and protocols for fast and robust distributed mesh provisioning and restorationTsuneo Nakata. bell, 7(3):23-39, 2003. [doi]

2002

An Object-Oriented Design Process for System-on-Chip Using UMLTsuneo Nakata, Akio Matsuda, Minoru Shoji, Shinya Kuwamura, Qiang Zhu. isss 2002: 249-254 [doi]

Functional Verification of System on Chips-Practices, Issues and Challenges (Tutorial Abstract)Subir K. Roy, S. Ramesh, Supratik Chakraborty, Tsuneo Nakata, Sreeranga P. Rajan. vlsid 2002: 11-13 [doi]

2001

A Method of Static Compaction of Test StimuliKwame Osei Boateng, Hideaki Konishi, Tsuneo Nakata. ats 2001: 137-144 [doi]

2000

Dataflow Analysis for Resource Contention and Register Leakage PropertiesSubir K. Roy, Hiroaki Iwashita, Tsuneo Nakata. vlsid 2000: 418-423 [doi]

Formal verification based on assume and guarantee approach - a case study (short paper)Subir K. Roy, Hiroaki Iwashita, Tsuneo Nakata. aspdac 2000: 77-80 [doi]

1998

An approach to verify a large scale system-on-a-chip using symbolic model checkingKoichiro Takayama, Taizo Satoh, Tsuneo Nakata, Fumiyasu Hirose. In ICCD. 1998: 308-313 [doi]

1997

Forward model checking techniques oriented to buggy designsHiroaki Iwashita, Tsuneo Nakata. iccad 1997: 400-404 [doi]

1996

CTL model checking based on forward state traversalHiroaki Iwashita, Tsuneo Nakata, Fumiyasu Hirose. iccad 1996: 82-87 [doi]

1994

Automatic test program generation for pipelined processorsHiroaki Iwashita, Satoshi Kowatari, Tsuneo Nakata, Fumiyasu Hirose. iccad 1994: 580-583 [doi]

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