Abstract is missing.
- Towards a natural language interface for CADTariq Samad, Stephen W. Director. 2-8 [doi]
- Unified user interface for a CAD systemAlberto Di Janni, Margherita Italiano. 9-15 [doi]
- A design by example regular structure generatorCyrus Bamji, Charles E. Hauck, Jonathan Allen. 16-22 [doi]
- A technique for distributed execution of design automation toolsS. C. Hughes, D. B. Lewis, C. J. Rimkus. 23-30 [doi]
- ACORN: a local customization approach to DCVS physical designEllen J. Yoffa, Peter S. Hauge. 32-38 [doi]
- Generation of layouts from MOS circuit schematics: a graph theoretic approachTak-Kwong Ng, S. Lennart Johnsson. 39-45 [doi]
- Automatic layout algorithms for function blocks of CMOS gate arraysShigeo Noda, Hitoshi Yoshizawa, Etsuko Fukuda, Haruo Kato, Hiroshi Kawanishi, Takashi Fujii. 46-52 [doi]
- Systematic and optimized layout of MOS cellsGabriele Saucier, Ghislaine Thuau. 53-61 [doi]
- MCNC s vertically integrated symbolic design systemC. Durward Rogers, Jonathan B. Rosenberg, Stephen W. Daniel. 62-68 [doi]
- A fully automatic hierarchical compactorGeorge Entenman, Stephen W. Daniel. 69-75 [doi]
- The VIVID system approach to technology independence: the matster technology file systemPhillip Smtih, Stephen W. Daniel. 76-81 [doi]
- Auto-interactive schematics to layout translationJonathan B. Rosenberg. 82-87 [doi]
- Importance of standards (tutorial session)Al Lowenstein, Greg Winter. 88-93 [doi]
- Computer aided (CA) tools integration and related standards development in a multi-vendor universe (panel session)Roger J. Pachter. 94-95 [doi]
- Mechanical design/analysis integration on Apollo workstationsJohn A. Pierro, George F. Donnellan. 96-101 [doi]
- Custom microcomputers for CAD optimization softwareRaj Abraham. 102-110 [doi]
- A database management approach to CAD/CAM systems integrationYehuda E. Kalay. 111-116 [doi]
- Two-dimensional router for double layer layoutMalgorzata Marek-Sadowska. 117-123 [doi]
- Timing influenced layout designMichael Burstein, Mary N. Youssef. 124-130 [doi]
- An algorithm for one and half layer channel routingJ. N. Song, Y. K. Chen. 131-136 [doi]
- A new algorithm for third generation circuit simulators: the one-step relaxation methodB. Hennion, P. Senn, D. Coquelle. 137-143 [doi]
- Macromodeling of digital MOS VLSI CircuitsMark D. Matson. 141-151 [doi]
- ACTAS: an accurate timing analysis system for VLSIMichiaki Muraoka, Hirokazu Iida, Hideyuki Kikuchihara, Michio Murakami, Kazuyuki Hirakawa. 152-158 [doi]
- Engineering workstation applications to systems design (panel session): life above the ICCecelia Jankowski. 159-160 [doi]
- Early verification of prototype tooling for IC designs (tutorial)J. P. Simmons Jr.. 161 [doi]
- Decomposition of logic networks into siliconSteven T. Healey, Daniel D. Gajski. 162-168 [doi]
- SWAMI: a flexible logic implementation systemChristopher Rowen, John L. Hennessy. 169-175 [doi]
- Yet another silicon compilerDavid E. Krekelberg, Gerald E. Sobelman, Chu S. Jhon. 176-182 [doi]
- ALLENDE: a procedural language for the hierarchical specification of VLSI layoutsJosé Monteiro da Mata. 183-189 [doi]
- Design for testability in a silicon compilation environmentH. S. Fung, S. Hirschhorn, R. Kulkarni. 190-196 [doi]
- PLATYPUS: a PLA test pattern generation toolRuey-Sing Wei, Alberto L. Sangiovanni-Vincentelli. 197-203 [doi]
- PROTEST: a tool for probabilistic testability analysisHans-Joachim Wunderlich. 204-211 [doi]
- PATEGE: an automatic DC parametric test generation system for series gated ECL circuitsTakuji Ogihara, Shuichi Saruyama, Shinichi Murai. 212-218 [doi]
- Workstations (panel discussion): a complete solution to the VLSI designer?Prathima Agrawal, Frederick L. Cohen, Chet A. Palesko, Hung-Fai Stephen Law, Mark Miller, Mike Price, David W. Smith, Nicholas P. Van Brunt. 219-225 [doi]
- Course, video, and manual dexterity (tutorial): tailoring training to CAD usersFrancine S. Frome. 226-231 [doi]
- The Silc silicon compiler: language and featuresTimothy Blackman, Jeffrey Fox, Christopher Rosebrugh. 232-237 [doi]
- A functional language for description and design of digital systems: sequential constructsF. Meshkinpour, Milos D. Ercegovac. 238-244 [doi]
- Layla: a VLSI layout languageWarren E. Cory. 245-251 [doi]
- The VLSI design automation assistant: what s in a knowledge baseThaddeus J. Kowalski, Donald E. Thomas. 252-258 [doi]
- A knowledge based system for selecting a test methodology for a PLAMelvin A. Breuer, Xi-an Zhu. 259-265 [doi]
- WEAVER: a knowledge-based routing expertRostam Joobbani, Daniel P. Siewiorek. 266-272 [doi]
- Generalised CMOS-a technology independent CMOS IC design styleNeil Bergmann. 273-278 [doi]
- Technology tracking for VLSI layout design toolsKung-Chao Chu, Y. Edmund Lien. 279-285 [doi]
- Magic s circuit extractorWalter S. Scott, John K. Ousterhout. 286-292 [doi]
- Hierarchical analysis of IC artwork with user defined abstraction rulesLouis Scheffer, Ronny Soetarman. 293-298 [doi]
- An algorithm for design rule checking on a multiprocessorGeorge E. Bier, Andrew R. Pleszkun. 299-304 [doi]
- Resistance calculation from mask artwork data by finite element methodErich Barke. 305-311 [doi]
- A data architecture for an uncertain design and manufacturing environmentThomas R. Smith. 312-318 [doi]
- CMU-CAM systemAndrzej J. Strojwas. 319-325 [doi]
- Cost-effective computer-aided manufacturing of prototype partsKeith S. Reid-Green. 326-329 [doi]
- A knowledge based planning system for mechanical assembly usign robotsKai-Hsiung Chang, William G. Wee. 330-336 [doi]
- Layout design-lessons from the Jedi designer (tutorial session)Susan L. Taylor, Roderic Beresford, Theodore Sabety. 337 [doi]
- MuSiC: an event-flow computer for fast simulation of digital systemsWinfried Hahn, Kristian Fischer. 338-344 [doi]
- A hardware engine for analogue mode simulation of MOS digital circuitsDavid M. Lewis. 345-351 [doi]
- The STE-264 accelerated electronic CAD systemPatrick M. Hefferan, Robert J. Smith II, Val Burdick, Donald L. Nelson. 352-358 [doi]
- Hardware acceleration of gate array layoutPhilip M. Spira, Carl Hage. 359-366 [doi]
- Synthesis by delayed binding of decisionsJayanth V. Rajan, Donald E. Thomas. 367-373 [doi]
- Linking the behavioral and structural dominis of representation in a synthesis systemRobert L. Blackburn, Donald E. Thomas. 374-380 [doi]
- An automated data path synthesizer for a canonic structure, implementable in VLSIKumar Ramayya, Anshul Kumar, Surendra Prasad. 381-387 [doi]
- Automatic generation of digital system schematic diagramsAnjali Arya, Anshul Kumar, V. V. Swaminathan, Amit Misra. 388-395 [doi]
- A subjective review of compaction (tutorial session)Y. Eric Cho. 396-404 [doi]
- Looking for Mr. Turnkey Michael R. Wayne, Susan M. Braun. 405-409 [doi]
- Relational and entity-relationship model databases and specialized design files in VLSI designMarianne Winslett, Richard Berlin, Thomas H. Payne, Gio Wiederhold. 410-416 [doi]
- An architecture design and assessment system for software/hardware codesignConnie U. Smith, Geoffrey A. Frank, John L. Cuadrado. 417-424 [doi]
- Yield analysis modelingSteve Perry, Mike Mitchell, D. Pilling. 425-428 [doi]
- A circuit comparison system for bipolar linear LSITakeshi Sakata, Aritoyo Kishimoto. 429-434 [doi]
- Silicon compilation of gate array basesRussel L. Steinweg, Susan J. Aguirre, Kerry Pierce, Scott Nance. 435-438 [doi]
- A hierarchical gate array architecture and design methodologyM. Iachponi, D. Vail, S. Bierly, A. Ignatowski. 439-442 [doi]
- ALPS2: a standard cell layout system for double-layer metal technologyC. P. Hsu, B. N. Tien, K. Chow, R. A. Perry, J. Tang. 443-448 [doi]
- PLINT layout system for VLSI chipsHart Anway, Greg Farnham, Rebecca Reid. 449-452 [doi]
- A model of design representation and synthesisRobert A. Walker, Donald E. Thomas. 453-459 [doi]
- An adaptive and evolutive tool for describing general hierarchical models, based on frames and demonsN. Giambiasi, B. MacGee, R. L Bath, L. Demians d Archimbaud, C. Delorme, P. Roux. 460-467 [doi]
- A behavioral modeling system for cell compilersJames C. Althoff, Robert D. Shur. 468-474 [doi]
- Synthesis techniques for digital systems designRaul Camposano. 475-481 [doi]
- Integrating stochastic performance analysis with system design toolsCharles W. Rose, Marcus Buchnen, Yatin Trivedi. 482-488 [doi]
- Synthesis of optimal clocking schemesNohbyung Park, Alice C. Parker. 489-495 [doi]
- Future directions for DA machine research (panel session)Rob A. Rutenbar. 496-497 [doi]
- The impact of technological advances on programmable controller s(tutorial session)Robert P. Collins, William J. Ketelhut. 498-502 [doi]
- A routing procedure for mixed array of custom macros and standard cellsHidekazu Terai, Michiyoshi Hayase, Tokinori Kozawa. 503-508 [doi]
- A method for gridless routing of printed circuit boardsA. C. Finch, K. J. Mackenzie, G. J. Balsdon, G. Symonds. 509-515 [doi]
- Layering algorithms for single row routingSangyong Han, Sartaj Sahni. 516-522 [doi]
- An expert systems approach to completing partially routed printed circuit boardsRobert Leonard Joseph. 523-528 [doi]
- MIDAS: integrated CAD for total system designW. M. Budney, S. K. Holewa. 529-535 [doi]
- Integrated design system for supercomputer SX-1/SX-2Shigenobu Suzuki, Kazutoshi Takahashi, Takao Sugimoto, Mikio Kuwata. 536-542 [doi]
- Integrated VLSI CAD systems at Digital Equipment CorporationA. F. Hutchings, R. J. Bonneau, W. M. Fisher. 543-548 [doi]
- The ITT VLSI design system: CAD integration in a multi-national environmentN. J. Elias, R. J. Byrne, A. D. Close, R. M. McDermott. 549-553 [doi]
- Computer aided design for analog applications (panel session): an assessmentJohn Lowell. 554 [doi]
- Software quality assurance for CAD (tutorial)E. T. Grinthal. 555-561 [doi]
- Development concerns for a software design quality expert systemChristopher W. Pidgeon, Peter A. Freeman. 562-568 [doi]
- ICHABOD: a data base manager for design automation applicationsHoward B. Schutzman. 569-576 [doi]
- A module for improving data access and management in an integrated CAD environmentG. P. Barabino, G. S. Barabino, G. Bisio, M. Marchesi. 577-583 [doi]
- Star s envoling design environment: a user s perspective on CAEGary B. Goates, Patrick M. Hefferan, Robert J. Smith II, Randy Harris. 584-590 [doi]
- A case study in process independenceNatalie Royal, John Hunter, Irene Buchanan. 591-596 [doi]
- Portability in silicon CAEJohn P. Gray, John Hunter. 597-601 [doi]
- An analytical algorithm for placement of arbitrarily sized rectangular blocksLu Sha, Robert W. Dutton. 602-608 [doi]
- Near-optimal placement using a quadratic objective functionJohn P. Blanks. 609-615 [doi]
- Knowledge-based placement technique for printed wiring boardsGotaro Odawara, Kazuhiko Iijima, Kazutoshi Wakabayashi. 616-622 [doi]
- An object-oriented swicth-level simulatorC. Roy, L.-P. Demers, Eduard Cerny, Jan Gecsei. 623-629 [doi]
- An extensible object-oriented mixed-mod functional simulation systemRichard H. Lathrop, Robert S. Kirk. 630-636 [doi]
- Modeling switch-level simulation using data flowV. Ashok, Roger L. Costello, P. Sadayappan. 637-644 [doi]
- Building a layered database for design automationRobert V. Zara, David R. Henke. 645-651 [doi]
- Effective data management for VLSI designPaul McLellan. 652-657 [doi]
- CADTOOLS: a CAD algorithm development systemEric Schell, M. Ray Mercer. 658-666 [doi]
- The McBOOLE logic minimizerMichel Dagenais, Vinod K. Agarwal, Nicholas C. Rumin. 667-673 [doi]
- Multiple output minimizationPrathima Agrawal, Vishwani D. Agrawal, Nripendra N. Biswas. 674-680 [doi]
- Electrical optimization of PLAsKye S. Hedlund. 681-687 [doi]
- Symbolic manipulation of Boolean functions using a graphical representationRandal E. Bryant. 688-694 [doi]
- Hierarchical circuit verificationYiwan Wong. 695-701 [doi]
- Efficient netlist comparison using hierarchy and randomizationJ. Doug Tygar, Ron Ellickson. 702-708 [doi]
- Analysis of timing failures due to random AC defects in VLSI modulesNandakumar N. Tendolkar. 709-714 [doi]
- Performance evaluation of FMOSSIM, a concurrent switch-level fault simulatorRandal E. Bryant, Michael Dd. Schuster. 715-719 [doi]
- Functional fault modeling and simulation for VLSI devicesAnil K. Gupta, James R. Armstrong. 720-726 [doi]
- The ADAM advanced design automation system: overview, planner and natural language interfaceJohn J. Granacki, David Knapp, Alice C. Parker. 727-730 [doi]
- Diagrammatic function description of microprocessor and data-flow processorGotaro Odawara, Masahiro Tomita, Ichiro Ogata. 731-734 [doi]
- Switch-level simulation of VLSI using a special-purpose data-driven computerEdward H. Frank. 735-738 [doi]
- PHIPLA-a new algorithm for logic minimizationPeter J. M. van Laarhoven, Emile H. L. Aarts, Marc Davio. 739-743 [doi]
- A heuristic algorithm for PLA block foldingY. S. Kuo, C. Chen, T. C. Hu. 744-747 [doi]
- Experiments with simulated annealingSurendra Nahar, Sartaj Sahni, Eugene Shragowitz. 748-752 [doi]
- An abstract machine data structure for non-procedural functional modelsRobert V. Zara, Kevin Rose, Ghulam Nurie, Harish Sarin. 753-756 [doi]
- A unified approach to simulation and timing verification at the functional levelVighneswara Row Mokkarala, Antony Fan, Ravi Apte. 757-761 [doi]
- A transistor-level logic-with-timing simulator for MOS circuitsThomas J. Schaefer. 762-765 [doi]
- PLAYER: a PLA design system for VLSI sYoshiyuki Koseki, Teruhiko Yamada. 766-769 [doi]
- The integration of an advanced gate array router into a fully automated design systemRobert Dwyer, Stephen Morris, Edward Bard, Daniel Green. 770-772 [doi]
- GAMMA: a fast prototype design, build, and test processLouise T. Lemaire. 773-776 [doi]
- Effective use of virtual grid compaction in macro-module generatorsDwight D. Hill, John P. Fishburn, Mary Diane Palmer Leland. 777-780 [doi]
- Algorithms for automatic transistor sizing in CMOS digital circuitsWilliam H. Kao, Nader Fathi, Chia-Hao Lee. 781-784 [doi]
- Automatic routing algorithm for VLSIHiroshi Andou, Ichiro Yamamoto, Yuuko Mori, Yutaka Koike, Kimikatsu Shouji, Kazuyuki Hirakawa. 785-788 [doi]
- Symbolic hierarchical artwork generation systemStef van Vlierberghe, Jeff Rijmenants, Walter Heyns. 789-793 [doi]
- The construction of minimal area power and ground nets for VLSI circuitsSalim U. Chowdhury, Melvin A. Breuer. 794-797 [doi]
- PLA driver selection: an analytic approachFred W. Obermeier, Randy H. Katz. 798-802 [doi]
- RTG: automatic register level test generatorSemyon Shteingart, Andrew W. Nagle, John Grason. 803-807 [doi]
- Simulation-free estimation of speed degradation in NMOS self-testing circuits for CAD applicationsAndrzej Krasniewski, Alexander Albicki. 808-811 [doi]
- Speed up techniques of logic simulationMasayuki Miyoshi, Yoshiharu Kazama, Osamu Tada, Yasuo Nagura, Nobutaka Amano. 812-815 [doi]
- Development of a timing analysis program for multiple clocked networkEdward Chan. 816-819 [doi]
- A functional partitioning expert system for test sequences generationC. Delorme, P. Roux, L. Demians d Archimbaud, N. Giambiasi, R. L Bath, B. MacGee, R. Charroppin. 820-824 [doi]
- Transistor level test generation for MOS circuitsMadhukar K. Reddy, Sudhakar M. Reddy, Prathima Agrawal. 825-828 [doi]
- Electronic CAD/CAM-is it revolution or evolution (tutorial session)Beth W. Tucker. 830-834 [doi]