Abstract is missing.
- The Role of Test in Circuits Built with Unreliable ComponentsAntonio Rubio. 3 [doi]
- The Future Is Low Power and TestT. W. Williams. 4 [doi]
- Safe Fault Collapsing Based on Dominance RelationsIrith Pomeranz, Sudhakar M. Reddy. 7-12 [doi]
- A Reliable Architecture for the Advanced Encryption StandardGiorgio Di Natale, M. Doulcier, Marie-Lise Flottes, Bruno Rouzeyre. 13-18 [doi]
- Bandwidth Analysis for Reusing Functional Interconnect as Test Access MechanismArdy van den Berg, Pengwei Ren, Erik Jan Marinissen, Georgi Gaydadjiev, Kees Goossens. 21-26 [doi]
- Analog Test Bus Infrastructure for RF/AMS Modules in Core-Based DesignVladimir A. Zivkovic, Frank van der Heyden, Guido Gronthoud, Frans de Jong. 27-32 [doi]
- Confidence Estimation in Non-RF to RF Correlation-Based Specification Test CompactionNathan Kupp, Petros Drineas, Mustapha Slamani, Yiorgos Makris. 35-40 [doi]
- Built-in Test of Frequency Modulated RF Transmitters Using Embedded Low-Pass FiltersRajarajan Senguttuvan, Hyun Choi, Donghoon Han, Abhijit Chatterjee. 41-46 [doi]
- Using Temperature as Observable of the Frequency Response of RF CMOS AmplifiersEduardo Aldrete-Vidrio, M. Amine Salhi, Josep Altet, Stéphane Grauby, Diego Mateo, H. Michel, L. Clerjaud, Jean-Michel Rampnoux, Antonio Rubio, Wilfrid Claeys, Stefan Dilhaire. 47-52 [doi]
- A Capture-Safe Test Generation Scheme for At-Speed Scan TestingX. Wen, Kohei Miyase, Seiji Kajihara, Hiroshi Furukawa, Yuta Yamato, Atsushi Takashima, Kenji Noda, H. Ito, Kazumi Hatayama, Takashi Aikyo, Kewal K. Saluja. 55-60 [doi]
- Temporally Extended High-Level Decision Diagrams for PSL Assertions SimulationMaksim Jenihhin, Jaan Raik, Anton Chepurov, Raimund Ubar. 61-68 [doi]
- On Bypassing Blocking Bugs during Post-Silicon ValidationEhab Anis Daoud, Nicola Nicolici. 69-74 [doi]
- Applying March Tests to K-Way Set-Associative Cache MemoriesSimone Alpe, Stefano Di Carlo, Paolo Prinetto, Alessandro Savino. 77-83 [doi]
- Hierarchical Code Correction and Reliability Management in Embedded nor Flash MemoriesBenoît Godard, Jean Michel Daga, Lionel Torres, Gilles Sassatelli. 84-90 [doi]
- Self-Programmable Shared BIST for Testing Multiple MemoriesSwapnil Bahl, Vishal Srivastava. 91-96 [doi]
- Bridge Defect Diagnosis for Multiple-Voltage DesignS. Saqib Khursheed, Paul M. Rosinger, Bashir M. Al-Hashimi, Sudhakar M. Reddy, Peter Harrod. 99-104 [doi]
- Diagnose Multiple Stuck-at Scan Chain FaultsYu Huang, Wu-Tung Cheng, Ruifeng Guo. 105-110 [doi]
- A Simulator of Small-Delay Faults Caused by Resistive-Open DefectsAlejandro Czutro, Nicolas Houarche, Piet Engelke, Ilia Polian, Mariane Comte, Michel Renovell, Bernd Becker. 113-118 [doi]
- Critical Path Selection for Delay Test Considering Coupling NoiseRajeshwary Tayade, Jacob A. Abraham. 119-124 [doi]
- Low Overhead Partial Enhanced Scan Technique for Compact and High Fault Coverage Transition Delay Test PatternsSeongmoon Wang, Wenlong Wei. 125-130 [doi]
- Accelerated Shift Registers for X-tolerant Test Data CompactionMartin Hilscher, Michael Braun, Michael Richter, Andreas Leininger, Michael Gössel. 133-139 [doi]
- An Innovative and Low-Cost Industrial Flow for Reliability Characterization of SoCsDavide Appello, Paolo Bernardi, R. Cagliesi, M. Giancarlini, Michelangelo Grosso. 140-145 [doi]
- An Improved Algorithm to Identify the Test Stimulus in Histogram-Based A/D Converter TestingEsa Korhonen, Juha Kostamovaara. 149-154 [doi]
- Jitter Decomposition in High-Speed Communication SystemsQingqi Dou, Jacob A. Abraham. 157-162 [doi]
- Risks for Signal Integrity in System in Package and Possible RemediesDaniele Rossi, Paolo Angelini, Cecilia Metra, Giovanni Campardo, Gianpietro P. Vanalli. 165-170 [doi]
- Function-Inherent Code Checking: A New Low Cost On-Line Testing Approach for High Performance Microprocessor Control LogicCecilia Metra, Daniele Rossi, Martin Omaña, Abhijit Jas, Rajesh Galivanche. 171-176 [doi]
- Tunable Transient Filters for Soft Error Rate Reduction in Combinational CircuitsQuming Zhou, Mihir R. Choudhury, Kartik Mohanram. 179-184 [doi]
- Selective Hardening in Early Design StepsChristian G. Zoellin, Hans-Joachim Wunderlich, Ilia Polian, Bernd Becker. 185-190 [doi]
- Convolutional Coding for SEU mitigationLaura Frigerio, Matteo Alan Radaelli, Fabio Salice. 191-196 [doi]
- Adaptive Debug and Diagnosis without Fault DictionariesStefan Holst, Hans-Joachim Wunderlich. 199-204 [doi]