Table of Contents

• A New High Density and Very Low Cost Reprogrammable FPGA ArchitectureSinan Kaptanoglu, Greg Bakker, Arun Kundu, Ivan Corneillet, Ben Ting. 3-12 [doi]
• Hybrid Product Term and LUT Based Architectures Using Embedded Memory BlocksFrank Heile, Andrew Leaver. 13-16 [doi]
• Cut Ranking and Pruning: Enabling a General and Efficient FPGA Mapping SolutionJason Cong, Chang Wu, Yuzheng Ding. 29-35 [doi]
• Using Cluster-Based Logic Blocks and Timing-Driven Packing to Improve FPGA Speed and DensityAlexander Marquardt, Vaughn Betz, Jonathan Rose. 37-46 [doi]
• A Methodology for Fast FPGA FloorplanningJohn M. Emmert, Dinesh Bhatia. 47-56 [doi]
• FPGA Routing Architecture: Segmentation and Buffering to Optimize Speed and DensityVaughn Betz, Jonathan Rose. 59-68 [doi]
• Balancing Interconnect and Computation in a Reconfiguable Computing Array (or, why you don t really want 100 LUT utilization)André DeHon. 69-78 [doi]
• Configuration Cloning: Exploiting Regularity in Dynamic DSP ArchitecturesS. R. Park, Wayne Burleson. 81-89 [doi]
• Don t Care Discovery for FPGA Configuration CompressionZhiyuan Li, Scott Hauck. 91-98 [doi]
• A FPGA-Based Hardware Implementation of Generalized Profile Search Using Online ArithmeticEmeka Mosanya, Eduardo Sanchez. 101-111 [doi]
• Procedural Texture Mapping on FPGAsAndy Gean Ye, David M. Lewis. 112-120 [doi]
• HSRA: High-Speed, Hierarchical Synchroous Reconfigurable ArrayWilliam Tsu, Kip Macy, Atul Joshi, Randy Huang, Norman Walker, Tony Tung, Omid Rowhani, George Varghese, John Wawrzynek, André DeHon. 125-134 [doi]
• A Reconfigurable Arithmetic Array for Multimedia ApplicationAlan Marshall, Tony Stansfield, Igor Kostarnov, Jean Vuillemin, Brad L. Hutchings. 135-143 [doi]
• Memory Interfacing and Instruction Specification for Reconfigurable ProcessorsJeffrey A. Jacob, Paul Chow. 145-154 [doi]
• Trading Quality for Compile Time: Ultra-Fast Placement for FPGAsYaska Sankar, Jonathan Rose. 157-166 [doi]
• Satisfiability-Based Layout Revisited: Detailed Routing of Complex FPGAs vis Search-Based Boolean SATGi-Joon Nam, Karem A. Sakallah, Rob A. Rutenbar. 167-175 [doi]
• Multi-Terminal Net Routing for Partial Crossbar-Based Multi-FPGA SystemsAbdel Ejnioui, N. Ranganathan. 176-185 [doi]
• Circuit Partitioning for Dynamically Reconfigurable FPGAsHuiqun Liu, D. F. Wong. 187-194 [doi]
• Configuration Caching Vs Data Caching for Striped FPGAsDeepali Deshpande, Arun K. Somani, Akhilesh Tyagi. 206-214 [doi]
• String Natching on Nulticontext FPGAs Using Self-ReconfigurationReetinder P. S. Sidhu, Alessandro Mei, Viktor K. Prasanna. 217-226 [doi]
• Exploiting FPGA-Features During the Emulation of a Fast Reactive Embedded SystemKarlheinz Weiß, Thorsten Steckstor, Gernot Koch, Wolfgang Rosenstiel. 235-242 [doi]
• ATLANTIS - A Hybrid Approach Combining the Power of FPGA and RISC Processors Based on CompactPCIKlaus Kornmesser, Torsten Kuberka, Andreas Kugel, Reinhard Männer, Stephan Rühl, M. Sessler, Holger Singpiel. 245 [doi]
• 400-MHz Frequency Counter: A Case Study in Semi-Synchronous DesignBernie New, Peter Alfke. 245 [doi]
• Architecture Considerations for Mixed Signals FPGAsLuigi Carro. 245 [doi]
• Dynamically Programmable Cache Evaluation and VirtualizationMouna Nakkar, David G. Bentlage, John Harding, David Schwartz, Paul D. Franzon, Thomas M. Conte. 246 [doi]
• A Computational Intelligence Based Coarse-Grained Reconfigurable ElementC. Hart Poskar, Peter J. Czezowski, Robert D. McLeod. 246 [doi]
• Design Issues in the Development of a JAVA-Processor for Small Embedded ApplicationsHagen Ploog, Tino Rachui, Dirk Timmermann. 246 [doi]
• Efficient Support of Hardware Debugging Through FPGA Physical Design PartitioningJohn Lach, William H. Mangione-Smith, Miodrag Potkonjak. 247 [doi]
• Exploiting Early Partial Reconfiguration of Run-Time Reconfigurable FPGAs in Embedded Systems DesignByungil Jeong, Sungjoo Yoo, Kiyoung Choi. 247 [doi]
• FPGA Design Experiences Using the CSELT VIP (TM) LibraryEnrica Filippi, A. Montanaro, M. Paolini, M. Turolla. 248 [doi]
• FPGA-Targeted Development System for Embedded ApplicationsValery Sklyarov, J. Fonseca, Ricardo Sal Monteiro, Arnaldo Oliveira, Andreia Melo, Nuno Lau, Konstantin Kondratjuk, Iouliia Skliarova, Paulo A. C. S. Neves, António de Brito Ferrari. 248 [doi]
• FPGA Based Computer Vision CameraA. Lecerf, F. Vachon, D. Ouellet, Miguel Arias-Estrada. 248 [doi]
• Hardware/Software Partitioning Between Microprocessor and Reconfigurable HardwareM. Anand, Sanjiv Kapoor, M. Balakrishnan. 249 [doi]
• High-Performance 2-D FPGA DCTs Using Polynomial TransformsChris Dick. 249 [doi]
• High-Performance Low-Cost Implementation of Two-Dimensional DCT Processor nn FPGAL. Naviner, Jean-Luc Danger, C. Laurent. 249 [doi]
• Implementing an Artificial CPG Using Fine-Grain FPGAsZhijun Yang, Felipe M. G. França. 250 [doi]
• Hierarchical Placement Directives for Parametric IP BlocksJames Hwang, Cameron Patterson, Sujoy Mitra. 250 [doi]
• Partitioning Large Designs by Filling PFGA Devices with Hierarchy BlocksHelena Krupnova, Gabriele Saucier. 251 [doi]
• A Method for Implementing Fractal Image Compression on Reconfigurable ArchitectureAkihiro Matsuura, Hidehisa Nagano, Akira Nagoya. 251 [doi]
• Module Generation of High Performance FPGA-Based MultipliersKun-Ming Ho, Allen C.-H. Wu. 251 [doi]
• Run-Time Parameterizable CoresSteve Guccione, Delon Levi. 252 [doi]
• Prototyping Board and Development Environment for Rapid Prototyping of Real Time and Regular Digital Signal Processing ApplicationPhilippe Soulard. 252 [doi]
• Self-Checking Logic Design for LUT-Based FPGAsParag K. Lala, A. L. Burress. 253 [doi]
• Special Arithmetic Operations on FPGAsMatti Tommiska. 253 [doi]
• Throughput Optimization with Design Space Exploration During Partitioning for Multi-FPGA ArchitecturesVinoo Srinivasan, Ranga Vemuri. 253 [doi]
• Universal Switch Blocks for Three-Dimensional FPGA DesignGuang-Ming Wu, Michael Shyu, Yao-Wen Chang. 254 [doi]
• Unified Access to Heterogeneous Module GeneratorsAndreas Koch. 254 [doi]
• Towards Adaptable Hierarchical Placement for FPGAsFlorent de Dinechin, Wayne Luk, Steve McKeever. 254 [doi]
• Why a CAD-Verified FPGA Makes Routing so Simple and Fast! A Result of Co-Designing FPGAs and CAD AlgorithmsTakahiro Murooka, Atsushi Takahara, Toshiaki Miyazaki. 255 [doi]
• The X-MatchLITE FPGA-Based Data CompressorJose Luis Nunez, Claudia Feregrino, Stephen Bateman, Simon Jones. 255 [doi]