Table of Contents

• Physical Design Space ExplorationEphrem Wu, Inkeun Cho. 1-4 [doi]
• Using Source-Level Transformations to Improve High-Level Synthesis Debug and Validation on FPGAsJoshua S. Monson, Brad L. Hutchings. 5-8 [doi]
• High-Level Design Tools for Floating Point FPGAsDeshanand P. Singh, Bogdan Pasca, Tomasz S. Czajkowski. 9-12 [doi]
• Software-Driven Hardware DevelopmentMyron King, Jamey Hicks, John Ankcorn. 13-22 [doi]
• InTime: A Machine Learning Approach for Efficient Selection of FPGA CAD Tool ParametersNachiket Kapre, Harnhua Ng, Kirvy Teo, Jaco Naude. 23-26 [doi]
• Unlocking FPGAs Using High Level Synthesis Compiler TechnologiesFernando Martinez-Vallina, Henry Styles. 27 [doi]
• Enhancing Hardware Design Flows with MyHDLKeerthan Jaic, Melissa C. Smith. 28-31 [doi]
• Rapid Prototyping of Wireless Physical Layer Modules Using Flexible Software/Hardware Design FlowJames Chacko, Cem Sahin, Douglas Pfiel, Nagarajan Kandasamy, Kapil R. Dandekar. 32-35 [doi]
• The BEEcube Story: Lessons Learned from Running a FPGA Startup for the Past 7 YearsChen Chang. 36 [doi]
• Application of Specific Delay Window Routing for Timing Optimization in FPGA DesignsEvan Wegley, Qinhai Zhang. 37-45 [doi]
• Fine-Grained Interconnect SynthesisAlex Rodionov, David Biancolin, Jonathan Rose. 46-55 [doi]
• Delay-Bounded Routing for Shadow RegistersEddie Hung, Joshua M. Levine, Edward A. Stott, George A. Constantinides, Wayne Luk. 56-65 [doi]
• RapidSmith 2: A Framework for BEL-level CAD Exploration on Xilinx FPGAsTravis Haroldsen, Brent E. Nelson, Brad L. Hutchings. 66-69 [doi]
• Technology Mapping into General Programmable CellsAlan Mishchenko, Robert K. Brayton, Wenyi Feng, Jonathan W. Greene. 70-73 [doi]
• EURECA: On-Chip Configuration Generation for Effective Dynamic Data AccessXinyu Niu, Wayne Luk, Yu Wang 0002. 74-83 [doi]
• Energy-Efficient Discrete Signal Processing with Field Programmable Analog Arrays (FPAAs)Bai Yu, Mingjie Lin. 84-93 [doi]
• Expanding OpenFlow Capabilities with Virtualized Reconfigurable HardwareStuart Byma, Naif Tarafdar, Talia Xu, Hadi Bannazadeh, Alberto Leon-Garcia, Paul Chow. 94-97 [doi]
• Take the Highway: Design for Embedded NoCs on FPGAsMohamed S. Abdelfattah, Andrew Bitar, Vaughn Betz. 98-107 [doi]
• Enhancements in UltraScale CLB ArchitectureShant Chandrakar, Dinesh Gaitonde, Trevor Bauer. 108-116 [doi]
• Floating-Point DSP Block Architecture for FPGAsMartin Langhammer, Bogdan Pasca. 117-125 [doi]
• Superoptimized Memory Subsystems for Streaming ApplicationsJoseph G. Wingbermuehle, Ron K. Cytron, Roger D. Chamberlain. 126-135 [doi]
• MATCHUP: Memory Abstractions for Heap Manipulating ProgramsFelix Winterstein, Kermin Fleming, Hsin-Jung Yang, Samuel Bayliss, George A. Constantinides. 136-145 [doi]
• Impact of Memory Architecture on FPGA Energy ConsumptionEdin Kadric, David Lakata, André DeHon. 146-155 [doi]
• Design Space Exploration of L1 Data Caches for FPGA-Based Multiprocessor SystemsEric Matthews, Nicholas C. Doyle, Lesley Shannon. 156-159 [doi]
• Growing a Healthy FPGA EcosystemJohn Lockwood, Michael Adler, Dan Mansur, Derek Chiou, Mike Strickland, Jason Cong, Steve Teig. 160 [doi]
• Optimizing FPGA-based Accelerator Design for Deep Convolutional Neural NetworksChen Zhang, Peng Li, Guangyu Sun, Yijin Guan, Bingjun Xiao, Jason Cong. 161-170 [doi]
• Wavefront Skipping using BRAMs for Conditional Algorithms on Vector ProcessorsAaron Severance, Joe Edwards, Guy G. F. Lemieux. 171-180 [doi]
• On Data Forwarding in Deeply Pipelined Soft ProcessorsCheah Hui Yan, Suhaib Fahmy, Nachiket Kapre. 181-189 [doi]
• Mapping-Aware Constrained Scheduling for LUT-Based FPGAsMingxing Tan, Steve Dai, Udit Gupta, Zhiru Zhang. 190-199 [doi]
• Resource-Aware Throughput Optimization for High-Level SynthesisPeng Li, Peng Zhang, Louis-Noël Pouchet, Jason Cong. 200-209 [doi]
• Numerical Program Optimization for High-Level SynthesisXitong Gao, George A. Constantinides. 210-213 [doi]
• System-level Linking of Synthesised Hardware and Compiled Software Using a Higher-order Type SystemShane T. Fleming, David Thomas, George A. Constantinides, Dan R. Ghica. 214-217 [doi]
• Automatic Time-Redundancy Transformation for Fault-Tolerant CircuitsDmitry Burlyaev, Pascal Fradet, Alain Girault. 218-227 [doi]
• 200 MS/s ADC implemented in a FPGA employing TDCsHarald Homulle, Francesco Regazzoni, Edoardo Charbon. 228-235 [doi]
• 0.5-V Highly Power-Efficient Programmable Logic using Nonvolatile Configuration Switch in BEOLMakoto Miyamura, Toshitsugu Sakamoto, Yukihide Tsuji, Munehiro Tada, Naoki Banno, Koichiro Okamoto, Noriyuki Iguchi, Hiromitsu Hada. 236-239 [doi]
• Energy and Memory Efficient Mapping of Bitonic Sorting on FPGARen Chen, Sruja Siriyal, Viktor A. Prasanna. 240-249 [doi]
• Ramethy: Reconfigurable Acceleration of Bisulfite Sequence AlignmentJames Arram, Wayne Luk, Peiyong Jiang. 250-259 [doi]
• A Novel Method for Enabling FPGA Context-Switch (Abstract Only)Alban Bourge, Olivier Muller, Frédéric Rousseau. 261 [doi]
• FPGA Acceleration for Simultaneous Image Reconstruction and Segmentation based on the Mumford-Shah Regularization (Abstract Only)Wentai Zhang, Li Shen, Thomas Page, Guojie Luo, Peng Li, Peter Maaß, Ming Jiang, Jason Cong. 261 [doi]
• An Efficient and Flexible FPGA Implementation of a Face Detection System (Abstract Only)Hichem Ben Fakih, Ahmed Elhossini, Ben H. H. Juurlink. 261 [doi]
• Towards More Efficient Logic Blocks By Exploiting Biconditional Expansion (Abstract Only)Pierre-Emmanuel Gaillardon, Gain Kim, Xifan Tang, Luca Gaetano Amarù, Giovanni De Micheli. 262 [doi]
• Logic Gates in the routing network of FPGAs (Abstract Only)Elias Vansteenkiste, Berg Severens, Dirk Stroobandt. 262 [doi]
• Real-Time Obstacle Avoidance for Mobile Robots via Stereoscopic Vision Using Reconfigurable Hardware (Abstract Only)Martinianos Papadopoulos, Christos Ttofis, Christos Kyrkou, Theocharis Theocharides. 262 [doi]
• Cost-Effective Memory Architecture to Achieve Flexible Configuration and Efficient Data Transmission for Coarse-Grained Reconfigurable Array (Abstract Only)Chen Yang, Leibo Liu, Shouyi Yin, Shaojun Wei. 263 [doi]
• An Automated Design Framework for Floating Point Scientific Algorithms using Field Programmable Gate Arrays (FPGAs) (Abstract Only)Michaela E. Amoo, Youngsoo Kim, Vance Alford, Shrikant Jadhav, Naser I. El-Bathy, Clay S. Gloster Jr.. 263 [doi]
• Sequence-based In-Circuit Breakpoints for Post-Silicon Debug (Abstract Only)Yutaka Tamiya, Yoshinori Tomita, Toshiyuki Ichiba, Kaoru Kawamura. 263 [doi]
• Exploring Efficiency of Ring Oscillator-Based Temperature Sensor Networks on FPGAs (Abstract Only)Navid Rahmanikia, Amirali Amiri, Hamid Noori, Farhad Mehdipour. 264 [doi]
• Formal Verification ATPG Search Engine Emulator (Abstract Only)Gregory Ford, Aswin Krishna, Jacob A. Abraham, Daniel G. Saab. 264 [doi]
• Platform-Independent Gigabit Communication for Low-Cost FPGAs (Abstract Only)Ralf Salomon, Ralf Joost, Matthias Hinkfoth. 265 [doi]
• An FPGA Implementation of a Timing-Error Tolerant Discrete Cosine Transform (Abstract Only)Yaoqiang Li, Pierce I.-Jen Chuang, Andrew A. Kennings, Manoj Sachdev. 266 [doi]
• An FPGA-Based Accelerator for the 2D Implicit FDM and Its Application to Heat Conduction Simulations (Abstract Only)Yutaro Ishigaki, Ning Li, Yoichi Tomioka, Akihiko Miyazaki, Hitoshi Kitazawa. 266 [doi]
• A Parallel And Scalable Multi-FPGA based Architecture for High Performance Applications (Abstract Only)Venkatasubramanian Viswanathan, Rabie Ben Atitallah, Jean-Luc Dekeyser, Benjamin Nakache, Maurice Nakache. 266 [doi]
• A Mixed-Grained Reconfigurable Computing Platform for Multiple-Standard Video Decoding (Abstract Only)Leibo Liu, Yingjie Chen, Dong Wang, Min Zhu, Shouyi Yin, Shaojun Wei. 267 [doi]
• FPGA-based BLOB Detection Using Dual-pipelining (Abstract Only)Naoto Nojiri, Lin Meng, Katsuhiro Yamazaki. 267 [doi]
• FiT: An Automated Toolkit for Matching Processor Architecture to Applications (Abstract Only)Charles Mutigwe, Johnson Kinyua, Farhad Aghdasi. 267 [doi]
• 300 Thousand Gates Single Event Effect Hardened SRAM-based FPGA for Space Application (Abstract Only)Lei Chen 0010, Yuanfu Zhao, Zhiping Wen, Jing Zhou, Xuewu Li, Yanlong Zhang, Huabo Sun. 268 [doi]
• An FPGA Implementation of Multi-stream Tracking Hardware using 2D SIMD Array (Abstract Only)Ryota Takasu, Yoichi Tomioka, Takashi Aoki, Hitoshi Kitazawa. 268 [doi]
• Architecture of Reconfigurable-Logic Cell Array with Atom Switch: Cluster Size & Routing Fabrics (Abstract Only)Xu Bai, Yukihide Tsuji, Ayuka Morioka, Makoto Miyamura, Toshi Sakamoto, Munehiro Tada, Naoki Banno, Koichiro Okamoto, Noriyuki Iguchi, Hiromitsu Hada. 269 [doi]
• A Novel Method for FPGA Test Based on Partial Reconfiguration and Sorting Algorithm (Abstract Only)Xianjian Zheng, Fan Zhang, Lei Chen, Zhiping Wen, Yuanfu Zhao, Xuewu Li. 269 [doi]
• REPROC: A Dynamically Reconfigurable Architecture for Symmetric Cryptography (Abstract Only)Bo Wang, Leibo Liu. 269 [doi]
• A Novel Composite Method to Accelerate Control Flow on Reconfigurable Architecture (Abstract Only)Junbin Wang, Leibo Liu, Jianfeng Zhu, Shouyi Yin, Shaojun Wei. 270 [doi]
• An Embedded FPGA Operating System Optimized for Vision Computing (Abstract Only)ZhiLei Chai, Jin Yu, Zhibin Wang, Jie Zhang, Haojie Zhou. 271 [doi]
• FPGA Implementation of Trained Coarse Carrier Frequency Offset Estimation and Correction for OFDM Signals (Abstract Only)Marko Jacovic, James Chacko, Doug Pfeil, Nagarajan Kandasamy, Kapil R. Dandekar. 271 [doi]
• Acceleration of Synthetic Aperture Radar (SAR) Algorithms using Field Programmable Gate Arrays (FPGAs) (Abstract Only)Youngsoo Kim, William Harding, Clay S. Gloster Jr., Winser E. Alexander. 271 [doi]
• Silicon Verification using High-Level Design Tools (Abstract Only)Tomasz S. Czajkowski. 272 [doi]
• Energy-Efficient High-Order FIR Filtering through Reconfigurable Stochastic Processing (Abstract Only)Mohammed Alawad, Mingjie Lin. 272 [doi]
• A Hardware Implementation of a Unit for Geometric Algebra Operations With Parallel Memory Arrays (Abstract Only)Gerardo Soria García, Adrian Pedroza de la Cruz, Susana Ortega-Cisneros, Juan José Raygoza-Panduro, Eduardo Bayro-Corrochano. 272 [doi]
• A Novel Coefficient Address Generation Algorithm for Split-Radix FFT (Abstract Only)Zhuo Qian, Martin Margala. 273 [doi]
• Efficient Generation of Energy and Performance Pareto Front for FPGA Designs (Abstract Only)Sanmukh R. Kuppannagari, Viktor K. Prasanna. 273 [doi]
• RapidPath: Accelerating Constrained Shortest Path Finding in Graphs on FPGA (Abstract Only)Chao Wang, Xi Li, Qi Guo, Xuehai Zhou. 273 [doi]
• High Level Programming of Document Classification Systems for Heterogeneous Environments using OpenCL (Abstract Only)Nasibeh Nasiri, Oren Segal, Martin Margala, Wim Vanderbauwhede, Sai Rahul Chalamalasetti. 274 [doi]
• Low-Resource Bluespec Design of a Modular Acquisition and Stimulation System for Neuroscience (Abstract Only)Paulo Matias, Rafael Tuma Guariento, Lírio Onofre Baptista de Almeida, Jan Frans Willem Slaets. 274 [doi]
• Bridging Architecture and Programming for Throughput-Oriented Vision Processing (Abstract Only)Amir Momeni, Hamed Tabkhi, Gunar Schirner, David R. Kaeli. 275 [doi]
• MedianPipes: An FPGA based Highly Pipelined and Scalable Technique for Median Filtering (Abstract Only)Umer I. Cheema, Gregory Nash, Rashid Ansari, Ashfaq A. Khokhar. 275 [doi]
• An Automatic Design Flow for Hybrid Parallel Computing on MPSoCs (Abstract Only)Hongyuan Ding, Miaoqing Huang. 275 [doi]
• Optimized Fixed-Point FPGA Implementation of SVPWM for a Two-Level Inverter (Abstract Only)Danyal Mohammadi, Said Ahmed-Zaid, Nader Rafla. 276 [doi]
• Toward Wave Digital Filter based Analog Circuit Emulation on FPGA (Abstract Only)Wei Wu, Peng Gu, Yen-Lung Chen, Chien-Nan Liu, Sudhakar Pamarti, Chang Wu, Lei He. 276 [doi]
• Customizable and High Performance Matrix Multiplication Kernel on FPGA (Abstract Only)Jie Wang, Jason Cong. 276 [doi]
• Area Optimization of Arithmetic Units by Component Sharing for FPGAs (Abstract Only)Shao Lin S. T. Tang, Guy Lemieux. 276 [doi]
• On Implementation of LUT with Large Numbers of Inputs (Abstract Only)Masahiro Fujita. 277 [doi]
• FPGA Acceleration of Irregular Iterative Computations using Criticality-Aware Dataflow Optimizations (Abstract Only)Siddhartha, Nachiket Kapre. 277 [doi]
• Accelerating Complete Decision Support Queries Through High-Level Synthesis Technology (Abstract Only)Gorker Alp Malazgirt, Nehir Sonmez, Arda Yurdakul, Osman S. Unsal, Adrián Cristal. 277 [doi]
• Design of a Loeffler DCT using Xilinx Vivado HLS (Abstract Only)Seung Yeol Baik, Seokjin Jeong, Hyeong-Cheol Oh. 278 [doi]